CXSD62117双通道电压模式和同步PWM控制器驱动双N通道mosfet两个通道均采用180度相移
发表时间:2020-04-24
浏览次数:311

目录Lp2嘉泰姆

1.产品概述                       2.产品特点Lp2嘉泰姆
3.应用范围                       4.下载产品资料PDF文档 Lp2嘉泰姆
5.产品封装图                     6.电路原理图                   Lp2嘉泰姆
7.功能概述                        8.相关产品

一,产品概述(General Description)         Lp2嘉泰姆
        The CXSD62117 is a dual channel voltage mode and syn-chronousLp2嘉泰姆
PWM controller which drives dual N-channel MOSFETs. The two channelsLp2嘉泰姆
are operated with 180 de-gree phase shift.The device integrates all of theLp2嘉泰姆
control, monitoring, and protecting functions into a single package; providesLp2嘉泰姆
two controlled power output with over-voltage, over-temperature, andLp2嘉泰姆
over-current protections.Lp2嘉泰姆
       The CXSD62117 provides excellent regulation for output load variation.Lp2嘉泰姆
The internal 1.0V temperature-compen- sated reference voltage providesLp2嘉泰姆
high accuracy of 0.8% over line and temperature. The device includes aLp2嘉泰姆
50kHz free-running triangle-wave oscillator that is adjustable from 50kHzLp2嘉泰姆
to 400kHz.The CXSD62117 has been equipped with excellent pro-tectionLp2嘉泰姆
functions: POR, OCP, UVP, and OVP protections.The Power-On-Reset (POR)Lp2嘉泰姆
circuit can monitor the VCC and OCSET voltage to make sure the supplyLp2嘉泰姆
voltage ex-ceeds their threshold voltage while the controller is running. TheLp2嘉泰姆
Over-Current Protection (OCP) monitors the output current by using theLp2嘉泰姆
voltage drop across the high side MOSFET’s RDS(ON). When the outputLp2嘉泰姆
current reaches the trip point, the controller will be latched. Under-VoltageLp2嘉泰姆

Protection (UVP) and Over-Voltage Protection (OVP) moni-tor the FBLp2嘉泰姆
voltage to protect CXSD62117 from burnout when output voltage isLp2嘉泰姆
under 50% or over 120% of normal out-put voltage. The CXSD62117Lp2嘉泰姆
is available in SOP-20 package.Lp2嘉泰姆

二.产品特点(Features)Lp2嘉泰姆
Single 12V Power Supply RequiredLp2嘉泰姆
Excellent Output Voltage RegulationLp2嘉泰姆
- 1.0V±0.8% Internal Reference Over Line and TemperatureLp2嘉泰姆
Simple Single Loop Control DesignLp2嘉泰姆
- Voltage Mode PWM Control 0~100% Duty RatioLp2嘉泰姆
Programmable Frequency Range from 50kHz toLp2嘉泰姆
400kHz (Constant 50kHz when Floating)Lp2嘉泰姆
Integrated Soft-Start and Soft-Off (Patent Pending)Lp2嘉泰姆
Support Pre-Biased Power-OnLp2嘉泰姆
Both Channel with 180o Phase ShiftLp2嘉泰姆
Integrated Boot-Strap DiodeLp2嘉泰姆
Over-Current ProtectionLp2嘉泰姆
- Sense High Side MOSFET’s RDS(ON)Lp2嘉泰姆
120% Over-Voltage ProtectionLp2嘉泰姆
50% Under-Voltage ProtectionLp2嘉泰姆
Over-Temperature ProtectionLp2嘉泰姆
Available in SOP-20 PackageLp2嘉泰姆
Lead Free and Green Devices Available (RoHS Compliant)Lp2嘉泰姆
三,应用范围 (Applications)Lp2嘉泰姆
SMPSLp2嘉泰姆

四.下载产品资料PDF文档 Lp2嘉泰姆

需要详细的PDF规格书请扫一扫微信联系我们,还可以获得免费样品以及技术支持Lp2嘉泰姆

 QQ截图20160419174301.jpgLp2嘉泰姆

 Lp2嘉泰姆

五,产品封装图 (Package)Lp2嘉泰姆

Lp2嘉泰姆

六.电路原理图Lp2嘉泰姆

blob.pngLp2嘉泰姆

七,功能概述Lp2嘉泰姆

Layout ConsiderationLp2嘉泰姆
In any high switching frequency converter, a correct lay-out is important to ensure proper operation of theLp2嘉泰姆
regulator. With power devices switching at 200kHz, the resulting current transient will cause voltage spike across the interconnecting impedance and parasitic circuit elements. As an example, consider the turn-off transition of the PWM MOSFET. Before turn-off, the MOSFET is car-rying the full load current. During turn-off, current stops flowing in the MOSFET and is free-wheeling by the lower MOSFET and parasitic diode. Any parasitic inductance of the circuit generates a large voltage spike during the switching interval. In general, using short and wide printed circuit traces should minimize interconnecting imped- ances and the magnitude of voltage spike. And signal and power grounds are to be kept separating till com-bined using the ground plane construction or single point grounding. Figure 8. illustrates the layout, with bold linesLp2嘉泰姆
Layout Consideration (Cont.)Lp2嘉泰姆

indicating high current paths; these traces must be short and wide. Components along the bold lines should beLp2嘉泰姆

placed lose together. Below is a checklist for your layout:- Keep the switching nodes (UGATE, LGATE, and PHASE)away from sensitive small signal nodes since these nodes are fast moving signals. Therefore, keep tracesLp2嘉泰姆
to these nodes as short as possible.Lp2嘉泰姆
- The traces from the gate drivers to the MOSFETs (UGATEand LGATE) should be short and wide.Lp2嘉泰姆

- Place the source of the high-side MOSFET and the drainof the low-side MOSFET as close as possible. Minimiz-ing the impedance with wide layout plane between the two pads reduces the voltage bounce of the node.Lp2嘉泰姆

- Decoupling capacitor, compensation component, the resistor dividers, and boot capacitors should be closeLp2嘉泰姆

their pins. (For example, place the decoupling ceramic capacitor near the drain of the high-side MOSFET asLp2嘉泰姆
close as possible. The bulk capacitors are also placed near the drain).Lp2嘉泰姆
- The input capacitor should be near the drain of the up-per MOSFET; the output capacitor should be near theLp2嘉泰姆
loads. The input capacitor GND should be close to the lower MOSFET GND.Lp2嘉泰姆
- The drain of the MOSFETs (VIN and PHASE nodes)should be a large plane for heat sinking.Lp2嘉泰姆
- The ROCSET resistance should be placed near the IC as close as possible.Lp2嘉泰姆
- The decoupling capacitor for VCC should be placed near the VCC and GND. CBOOT should be connected asLp2嘉泰姆
close to the BOOT and PHASE pins as possible. Lp2嘉泰姆

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