CXSD62116A|B|C电压模式固定300kHz开关频率和同步降压控制器两个电源电压模式
发表时间:2020-04-23
浏览次数:296

目录lZn嘉泰姆

1.产品概述                       2.产品特点lZn嘉泰姆
3.应用范围                       4.下载产品资料PDF文档 lZn嘉泰姆
5.产品封装图                     6.电路原理图                   lZn嘉泰姆
7.功能概述                        8.相关产品lZn嘉泰姆

一,产品概述(General Description)         lZn嘉泰姆
        The CXSD62116A/B/C is a voltage mode, fixed 300kHz-switching frequency,lZn嘉泰姆
and synchronous buck controller. The CXSD62116A/B/C allows wide input voltagelZn嘉泰姆
that is either a single 5~12V or two supply voltage(s) for various applications.lZn嘉泰姆
A power-on-reset (POR) circuit monitors the VCC supply voltage to preventlZn嘉泰姆
wrong logic controls. A built-in digital soft-start circuit prevents the outputlZn嘉泰姆
voltages from overshoot as well as limits the input current. An internallZn嘉泰姆
0.6V temperature-compensated reference voltage with high accuracy islZn嘉泰姆
designed to meet the requirement of low output voltage applications.lZn嘉泰姆
The CXSD62116A/B/C provides excellent output voltage regulations againstlZn嘉泰姆
load current variation.lZn嘉泰姆
     The controller’s over-current protection monitors the output currentlZn嘉泰姆
by using the voltage drops across the RDS(ON)of low-side MOSFET,lZn嘉泰姆
eliminating the need for a current sensing resistor that features highlZn嘉泰姆
efficiency and low cost.lZn嘉泰姆
     The CXSD62116A/B/C also integrates over-voltage protection (OVP) andlZn嘉泰姆
under-voltage protection circuit which moni-tors the FB voltage to preventlZn嘉泰姆
the PWM output from over and under voltage.lZn嘉泰姆
     The CXSD62116A/B/C is available in a simple SOP-8P package.lZn嘉泰姆
二.产品特点(Features)lZn嘉泰姆
Wide Operation Supply Voltage from 5V to 12VlZn嘉泰姆
Power-On-Reset Monitoring on VCC lZn嘉泰姆
Excellent Reference Voltage RegulationslZn嘉泰姆
- 0.6V Internal ReferencelZn嘉泰姆
- ±1% Over Temperature RangelZn嘉泰姆
Integrated Soft-StartlZn嘉泰姆
Automatic PSM/PWM ModeslZn嘉泰姆
Voltage Mode PWM Operation with 90% (Max.) Duty CyclelZn嘉泰姆
Under-Voltage ProtectionlZn嘉泰姆
Adjustable Over-Current Protection ThresholdlZn嘉泰姆
- Sensing the RDS(ON) of Low-Side MOSFETlZn嘉泰姆
Over-Voltage ProtectionlZn嘉泰姆
Under-Voltage ProtectionlZn嘉泰姆
Simple SOP-8P PackagelZn嘉泰姆
Lead Free and Green Devices AvailablelZn嘉泰姆
(RoHS Compliant)lZn嘉泰姆
三,应用范围 (Applications)lZn嘉泰姆
Graphic CardslZn嘉泰姆
DSL, Switch HUBlZn嘉泰姆
Wireless LanlZn嘉泰姆
Notebook ComputerlZn嘉泰姆
Mother BoardlZn嘉泰姆
LCD Monitor/TVlZn嘉泰姆

四.下载产品资料PDF文档 lZn嘉泰姆

需要详细的PDF规格书请扫一扫微信联系我们,还可以获得免费样品以及技术支持lZn嘉泰姆

 QQ截图20160419174301.jpglZn嘉泰姆

五,产品封装图 (Package)lZn嘉泰姆
lZn嘉泰姆
六.电路原理图lZn嘉泰姆

blob.pnglZn嘉泰姆
七,功能概述lZn嘉泰姆
Layout ConsiderationlZn嘉泰姆
In any high switching frequency converter, a correct lay-out is important to ensure proper operation of thelZn嘉泰姆
regulator. With power devices switching at 300kHz,the resulting current transient will cause voltage spike acrosslZn嘉泰姆
the interconnecting impedance and parasitic circuit elements. As an example, consider the turn-off transitionlZn嘉泰姆
of the PWM MOSFET. Before turn-off, the MOSFET is car rying the full load current. During turn-off, current stopslZn嘉泰姆
flowing in the MOSFET and is free-wheeling by the lower MOSFET and parasitic diode. Any parasitic inductance oflZn嘉泰姆
the circuit generates a large voltage spike during the switching interval. In general, using short and wide printedlZn嘉泰姆
circuit traces should minimize interconnecting imped-lZn嘉泰姆

Layout Consideration (Cont.)lZn嘉泰姆
ances and the magnitude of voltage spike. And signal and power grounds are to be kept separate till combinedlZn嘉泰姆

using ground plane construction or single point grounding. Figure 8. illustrates the layout, with bold lineslZn嘉泰姆
indicating high current paths; these traces must be short and wide. Components along the bold lines should belZn嘉泰姆

placed lose together. Below is a checklist for your layout:lZn嘉泰姆

- Keep the switching nodes (UGATE, LGATE, and PHASE) away from sensitive small signal nodes since theselZn嘉泰姆

nodes are fast moving signals. Therefore, keep traces to these nodes as short as possible.lZn嘉泰姆

- The traces from the gate drivers to the MOSFETs (UG and LG) should be short and wide.lZn嘉泰姆

- Place the source of the high-side MOSFET and the drain of the low-side MOSFET as close as possible. Minimiz-lZn嘉泰姆
ing the impedance with wide layout plane between the two pads reduces the voltage bounce of the node.lZn嘉泰姆
- Decoupling capacitor, compensation component, the resistor dividers, and boot capacitors should be closelZn嘉泰姆
their pins. (For example, place the decoupling ceramic capacitor near the drain of the high-side MOSFET aslZn嘉泰姆
close as possible. The bulk capacitors are also placed near the drain).lZn嘉泰姆
- The input capacitor should be near the drain of the up-per MOSFET; the output capacitor should be near thelZn嘉泰姆
loads. The input capacitor GND should be close to the output capacitor GND and the lower MOSFET GND.lZn嘉泰姆
- The drain of the MOSFETs (VIN and PHASE nodes) should be a large plane for heat sinking.lZn嘉泰姆
- The ROCSET resistance should be placed near the IC as close as possible.Close to IClZn嘉泰姆
Figure 8. Layout GuidelineslZn嘉泰姆

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