目录svr嘉泰姆

1.产品概述                       2.产品特点svr嘉泰姆
3.应用范围                       4.下载产品资料PDF文档 svr嘉泰姆
5.产品封装图                     6.电路原理图                   svr嘉泰姆
7.功能概述                        8.相关产品svr嘉泰姆

一,产品概述(General Description)     svr嘉泰姆

  The CXSD6297 is a voltage mode, fixed 300kHz switching frequency, synchronous buck converter. The CXSD6297 allows wide input voltage that is either a single 5V~12V or two supply voltage(s) for various applications. The power-on-reset (POR) circuit monitors the VCC supply voltage to prevent wrong logic controls. A built-in soft-start circuit prevents the output voltages from overshoot as well as limits the input current. An internal 0.8V tempera-ture-compensated reference voltage with high accuracy is designed to meet the requirement of low output volt-age applications. The CXSD6297 provides excellent out-put voltage regulations against load current variation.CXSD6297 is built in reference voltage offset function for applications that require adjusting supply voltage.The controller’s over-current protection monitors the out-put current by using the voltage drop across the RDS(ON) of low-side MOSFET, eliminating the need for a current sens-ing resistor that features high efficiency and low cost. In addition, the CXSD6297 also integrates excellent protec-tion functions, The over-voltage protection (OVP) , under-voltage protection (UVP) and over-temperature protec-tion (OTP). OVP circuit which monitors the FB voltage to prevent the PWM output from over voltage, and UVP cir-cuit which monitors the FB voltage to prevent the PWM output from under voltage or short circuit. OTP circuit whichsvr嘉泰姆
monitors the junction temperature to prevent over-heat-ing conditions.svr嘉泰姆
  The CXSD6297 is available in TDFN3x3-10 packagesvr嘉泰姆
二.产品特点(Features)svr嘉泰姆

1.)Wide 5V to 12V Supply Voltagesvr嘉泰姆
2.)Power-On-Reset Monitoring on VCCsvr嘉泰姆
3.)Excellent Output Voltage Regulationssvr嘉泰姆
     - 0.8V Internal Referencesvr嘉泰姆
     - ±1% Over Temperature Range svr嘉泰姆
4.)Integrated Soft-Startsvr嘉泰姆
5.)Voltage Mode PWM Operation with External Compensationsvr嘉泰姆
6.)Up to 90% Duty Ratio for Fast Transient Responsesvr嘉泰姆
7.)Constant Switching Frequencysvr嘉泰姆
    - 300kHz ±10%svr嘉泰姆
8.)Integrated Bootstrap Forward P-CH MOSFETsvr嘉泰姆
9.)Drive Dual Low Cost N-MOSFETs with Adaptive Dead Time Controlsvr嘉泰姆
10.)50% Under-Voltage Protectionsvr嘉泰姆
11.)125% Over-Voltage Protectionsvr嘉泰姆
12.)Adjustable Over-Current Protection Thresholdsvr嘉泰姆
    - Using the RDS(ON) of Low-Side MOSFETsvr嘉泰姆
13.)Shutdown Control by COMPsvr嘉泰姆
14.)Power Good Monitoringsvr嘉泰姆
15.)TDFN3x3-10 Packagesvr嘉泰姆
16.)Lead Free and Green Devices Available (RoHS Compliant)svr嘉泰姆
三,应用范围 (Applications)svr嘉泰姆

Graphic Cardssvr嘉泰姆
DSL, Switch HUBsvr嘉泰姆
Wireless Lansvr嘉泰姆
Notebook Computersvr嘉泰姆
Mother Boardsvr嘉泰姆
LCD Monitor/TVsvr嘉泰姆
四.下载产品资料PDF文档 svr嘉泰姆

需要详细的PDF规格书请扫一扫微信联系我们，还可以获得免费样品以及技术支持！svr嘉泰姆

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五,产品封装图 (Package)svr嘉泰姆

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六.电路原理图svr嘉泰姆

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七,功能概述svr嘉泰姆

Layout Considerationsvr嘉泰姆
In any high switching frequency converter, a correct lay-out is important to ensure proper operation of thesvr嘉泰姆
regulator. With power devices switching at 300kHz,the resulting current transient will cause voltage spike acrosssvr嘉泰姆
the interconnecting impedance and parasitic circuit elements. As an example, consider the turn-off transitionsvr嘉泰姆
of the PWM MOSFET. Before turn-off, the MOSFET is car-rying the full load current. During turn-off, current stopssvr嘉泰姆
flowing in the MOSFET and is free-wheeling by the lower MOSFET and parasitic diode. Any parasitic inductance ofsvr嘉泰姆
the circuit generates a large voltage spike during the switching interval. In general, using short and wide printedsvr嘉泰姆
circuit traces should minimize interconnecting impedsvr嘉泰姆
Layout Consideration (Cont.)svr嘉泰姆
ances and the magnitude of voltage spike. And signal and power grounds are to be kept separate till combinedsvr嘉泰姆
using ground plane construction or single point grounding. Figure 8. illustrates the layout, with bold linessvr嘉泰姆
indicating high current paths; these traces must be short and wide. Components along the bold lines should besvr嘉泰姆
placed lose together. Below is a checklist for your layout:svr嘉泰姆
- Keep the switching nodes (UGATE, LGATE, and PHASE) away from sensitive small signal nodes since thesesvr嘉泰姆
nodes are fast moving signals. Therefore, keep traces to these nodes as short as possible.svr嘉泰姆
 The traces from the gate drivers to the MOSFETs (UG and LG) should be short and wide.svr嘉泰姆
- Place the source of the high-side MOSFET and the drain of the low-side MOSFET as close as possible. Minimiz-svr嘉泰姆
ing the impedance with wide layout plane between the two pads reduces the voltage bounce of the node.svr嘉泰姆
 Decoupling capacitor, compensation component, the resistor dividers, and boot capacitors should be closesvr嘉泰姆
their pins. (For example, place the decoupling ceramic capacitor near the drain of the high-side MOSFET assvr嘉泰姆
close as possible. The bulk capacitors are also placed near the drain).svr嘉泰姆
- The input capacitor should be near the drain of the up-per MOSFET; the output capacitor should be near thesvr嘉泰姆
loads. The input capacitor GND should be close to the output capacitor GND and the lower MOSFET GND.svr嘉泰姆
- The drain of the MOSFETs (VIN and PHASE nodes) should be a large plane for heat sinking.svr嘉泰姆
The ROCSET resistance should be placed near the IC as close as possible.svr嘉泰姆

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