CXSU63137

CXSU63137集成了一个高性能升压转换器、两个线性调节器控制器、一个高压开关和一个(CXSU63137)、三个(CXSU63137)或五个(CXSU63137)大电流运算放大器,用于TFT-LCD应用。主升压调节器是电流模式、固定频率的PWM开关调节器。1.2兆赫的开关频率允许使用低剖面感应器和陶瓷电容器,以最小化液晶面板设计的厚度

2.6V至6.5V输入电源VGON和VGOFF的线性调节器控制器CXSU63137电流模式升压调节器大电流运算放大器

产品手册

产品订购

产品简介

目录hNv嘉泰姆

1.产品概述                       2.产品特点hNv嘉泰姆
3.应用范围                       4.下载产品资料PDF文档 hNv嘉泰姆
5.产品封装图                     6.电路原理图                   hNv嘉泰姆
7.功能概述                        8.相关产品hNv嘉泰姆

一,产品概述(General Description)         hNv嘉泰姆


           The CXSU63137 integrates with a high-performance step-up converter, two linear-regulator controllers, a high voltage switch and one (CXSU63137), three (CXSU63137) or five (CXSU63137) high current operational amplifiers for TFT-LCD applications.The main step-up regulator is a current-mode, fixed-fre-quency PWM switching regulator. The 1.2MHz switching frequency allows the usage of low-profile inductors and ceramic capacitors to minimize the thickness of LCD panel designs.hNv嘉泰姆
      The linear-regulator controllers used external transistors provide regulated the gate-driver of TFT-LCD VGON and VGOFF supplies.hNv嘉泰姆
The amplifiers are ideal for VCOM and VGAMMA applications, withhNv嘉泰姆
150m A peak output current drive, 10MHz bandwidth, and 13V/μs slewhNv嘉泰姆
rate. All inputs and outputs are rail-to-rail.hNv嘉泰姆
     The CXSU63137/1/2 is available in a tiny 5mm x 5mm 32-pin QFN package (TQFN5x5-32).hNv嘉泰姆
二.产品特点(Features)hNv嘉泰姆


· 2.6V to 6.5V Input Supply Range hNv嘉泰姆

· Current-Mode Step-Up Regulator hNv嘉泰姆

 - Fast Transient Response hNv嘉泰姆

 - 1.2MHz Fixed Operating Frequency hNv嘉泰姆

· ±1.5% High-Accuracy Output Voltage hNv嘉泰姆

· 3A, 20V, 0.25W Internal N-Channel MOSFET hNv嘉泰姆

· High Efficiency hNv嘉泰姆

· Low Quiescent Current (0.6mA Typical) hNv嘉泰姆

· Linear-Regulator Controllers for VGON and VGOFF hNv嘉泰姆

· High-performance Operational Amplifiers hNv嘉泰姆

 - ±150mA Output Short-Circuit CurrenthNv嘉泰姆

 - 13V/ms Slew Rate - 10MHz, -3dB Bandwidth hNv嘉泰姆

 - Rail-to-Rail Inputs/Outputs hNv嘉泰姆

· Fault-Delay Timer and Fault Latch for All Regulator Outputs hNv嘉泰姆

· Over-Temperature Protection hNv嘉泰姆

· Available in Compact 32-pin 5mmx5mm Thin QFN Package (TQFN5x5-32) hNv嘉泰姆

· Lead Free Available (RoHS Compliant)hNv嘉泰姆

三,应用范围 (Applications)hNv嘉泰姆


    TFT LCD Displays for MonitorshNv嘉泰姆
   TFT LCD Displays for Notebook ComputershNv嘉泰姆
   Automotive DisplayshNv嘉泰姆
四.下载产品资料PDF文档 hNv嘉泰姆


需要详细的PDF规格书请扫一扫微信联系我们,还可以获得免费样品以及技术支持hNv嘉泰姆

 QQ截图20160419174301.jpghNv嘉泰姆

五,产品封装图 (Package)hNv嘉泰姆


blob.pnghNv嘉泰姆
blob.pngPin Function DescriptionhNv嘉泰姆

PinhNv嘉泰姆

NamehNv嘉泰姆

Function DescriptionhNv嘉泰姆

CXSU63137hNv嘉泰姆

CXSU63137-1hNv嘉泰姆

CXSU63137-2hNv嘉泰姆

1hNv嘉泰姆

SRChNv嘉泰姆

SRChNv嘉泰姆

SRChNv嘉泰姆

Switch Input. Source of the internal high-voltage P-channel MOSFET. BypasshNv嘉泰姆
SRC to PGND with a minimum of 0.1μF capacitor closed to the pins.hNv嘉泰姆

2hNv嘉泰姆

REFhNv嘉泰姆

REFhNv嘉泰姆

REFhNv嘉泰姆

Reference voltage output. Bypass REF to AGND with a minimum ofhNv嘉泰姆
0.22μFcapacitor closed to the pins.hNv嘉泰姆

3hNv嘉泰姆

AGNDhNv嘉泰姆

AGNDhNv嘉泰姆

AGNDhNv嘉泰姆

Analog Ground for Step-Up Regulator and Linear Regulators. Connect tohNv嘉泰姆
power ground (PGND) underneath the IC.hNv嘉泰姆

4hNv嘉泰姆

PGNDhNv嘉泰姆

PGNDhNv嘉泰姆

PGNDhNv嘉泰姆

Power Ground for Step-Up Regulator. PGND is the source of the main step-uphNv嘉泰姆
n-channel power MOSFET. Connect PGND to the ground terminals of outputhNv嘉泰姆
capacitors through a short, wide PC board trace. Connect to analog groundhNv嘉泰姆
(AGND) underneath the IC.hNv嘉泰姆

5hNv嘉泰姆

OUT1hNv嘉泰姆

OUT1hNv嘉泰姆

OUT1hNv嘉泰姆

Output of Operational-Amplifier 1hNv嘉泰姆

6hNv嘉泰姆

NEG1hNv嘉泰姆

NEG1hNv嘉泰姆

NEG1hNv嘉泰姆

Inverting Input of Operational-Amplifier 1hNv嘉泰姆

7hNv嘉泰姆

POS1hNv嘉泰姆

POS1hNv嘉泰姆

POS1hNv嘉泰姆

Non-inverting Input of Operational-Amplifier 1hNv嘉泰姆

8hNv嘉泰姆

NChNv嘉泰姆

OUT2hNv嘉泰姆

OUT2hNv嘉泰姆

Output of Operational-Amplifier 2 of CXSU63137/CXSU63137. No internalhNv嘉泰姆
connected of CXSU63137.hNv嘉泰姆

9hNv嘉泰姆

NChNv嘉泰姆

NEG2hNv嘉泰姆

NEG2hNv嘉泰姆

Inverting Input of Operational-Amplifier 2 of CXSU63137/CXSU63137. No internalhNv嘉泰姆
connected of CXSU63137.hNv嘉泰姆

10hNv嘉泰姆

IChNv嘉泰姆

POS2hNv嘉泰姆

POS2hNv嘉泰姆

Non-inverting Input of Operational-Amplifier 2 of CXSU63137/CXSU63137. InternalhNv嘉泰姆
connected to GND of CXSU63137hNv嘉泰姆

11hNv嘉泰姆

BGNDhNv嘉泰姆

BGNDhNv嘉泰姆

BGNDhNv嘉泰姆

Analog Ground for Operational Amplifiers. Connect to power ground (PGND)hNv嘉泰姆
underneath the IC.hNv嘉泰姆

12hNv嘉泰姆

NChNv嘉泰姆

NChNv嘉泰姆

POS3hNv嘉泰姆

Non-inverting Input of Operational-Amplifier 3 of CXSU63137. No internalhNv嘉泰姆
connected of CXSU63137/CXSU63137.hNv嘉泰姆

13hNv嘉泰姆

NChNv嘉泰姆

NChNv嘉泰姆

OUT3hNv嘉泰姆

Output of Operational-Amplifier 3 of CXSU63137. No internal connected ofCXSU63137/CXSU63137.hNv嘉泰姆

14hNv嘉泰姆

SUPhNv嘉泰姆

SUPhNv嘉泰姆

SUPhNv嘉泰姆

Power Input of Operational Amplifiers. Typically connected to VMAIN. BypasshNv嘉泰姆
SUP to BGND with a 0.1μF capacitor.hNv嘉泰姆

15hNv嘉泰姆

NChNv嘉泰姆

POS3hNv嘉泰姆

POS4hNv嘉泰姆

Non-inverting Input of Operational-Amplifier 4 of CXSU63137. Non-invertinghNv嘉泰姆
Input of Operational-Amplifier 3 of CXSU63137. No internal connected ofCXSU63137.hNv嘉泰姆

16hNv嘉泰姆

NChNv嘉泰姆

NEG3hNv嘉泰姆

NEG4hNv嘉泰姆

Inverting Input of Operational-Amplifier 4 of CXSU63137. Inverting Input ofhNv嘉泰姆
Operational-Amplifier 3 of CXSU63137. No internal connected of CXSU63137.hNv嘉泰姆

17hNv嘉泰姆

NChNv嘉泰姆

OUT3hNv嘉泰姆

OUT4hNv嘉泰姆

Output of Operational-Amplifier 4 of CXSU63137. Output ofhNv嘉泰姆
Operational-Amplifier 3 of CXSU63137. No internal connected of CXSU63137.hNv嘉泰姆

18hNv嘉泰姆

IChNv嘉泰姆

IChNv嘉泰姆

POS5hNv嘉泰姆

Non-inverting Input of Operational-Amplifier 5 of CXSU63137. Internal connectedhNv嘉泰姆
to GND of CXSU63137/CXSU63137.hNv嘉泰姆

19hNv嘉泰姆

NChNv嘉泰姆

NChNv嘉泰姆

NEG5hNv嘉泰姆

Inverting Input of Operational-Amplifier 5 of CXSU63137. No internal connectedhNv嘉泰姆
of CXSU63137/CXSU63137.hNv嘉泰姆

20hNv嘉泰姆

NChNv嘉泰姆

NChNv嘉泰姆

OUT5hNv嘉泰姆

Output of Operational-Amplifier 5 of CXSU63137. No internal connected ofCXSU63137/CXSU63137.hNv嘉泰姆

21hNv嘉泰姆

LXhNv嘉泰姆

LXhNv嘉泰姆

LXhNv嘉泰姆

N-Channel Power MOSFET Drain and Switching Node. Connect the inductorhNv嘉泰姆
and Schottky diode to LX and minimize the trace area for lowest EMI.hNv嘉泰姆

22hNv嘉泰姆

INhNv嘉泰姆

INhNv嘉泰姆

INhNv嘉泰姆

Supply Voltage Input. Bypass IN to AGND with a 0.1μF capacitor. IN can rangehNv嘉泰姆
from 2.6V to 6.5V.hNv嘉泰姆

23hNv嘉泰姆

FBhNv嘉泰姆

FBhNv嘉泰姆

FBhNv嘉泰姆

Step-Up Regulator Feedback Input. Connect a resistive voltage-divider fromhNv嘉泰姆
the output (VMAIN) to FB to analog ground (AGND). Place the divider withinhNv嘉泰姆
5mm of FB.hNv嘉泰姆

24hNv嘉泰姆

COMPhNv嘉泰姆

COMPhNv嘉泰姆

COMPhNv嘉泰姆

Step-Up Regulator Error-Amplifier Compensation Point. Connect a series RChNv嘉泰姆
from COMP to AGND.hNv嘉泰姆

PinFunction DescriptionhNv嘉泰姆

PinhNv嘉泰姆

NamehNv嘉泰姆

Function DescriptionhNv嘉泰姆

CXSU63137hNv嘉泰姆

CXSU63137-1hNv嘉泰姆

CXSU63137-2hNv嘉泰姆

24hNv嘉泰姆

COMPhNv嘉泰姆

COMPhNv嘉泰姆

COMPhNv嘉泰姆

Step-Up Regulator Error-Amplifier Compensation Point. Connect a series RChNv嘉泰姆
from COMP to AGND.hNv嘉泰姆

25hNv嘉泰姆

FBPhNv嘉泰姆

FBPhNv嘉泰姆

FBPhNv嘉泰姆

Gate-On Linear-Regulator Feedback Input. Connect FBP to the center of ahNv嘉泰姆
resistive voltage-divider between the regulator output and AGND to set thehNv嘉泰姆
gate-on linear regulator output voltage. Place the resistive voltage-dividerhNv嘉泰姆
close to the pin.hNv嘉泰姆

26hNv嘉泰姆

DRVPhNv嘉泰姆

DRVPhNv嘉泰姆

DRVPhNv嘉泰姆

Gate-On Linear-Regulator Base Drive. Open drain of an internal n-channelhNv嘉泰姆
MOSFET. Connect DRVP to the base of an external PNP pass transistor.hNv嘉泰姆

27hNv嘉泰姆

FBNhNv嘉泰姆

FBNhNv嘉泰姆

FBNhNv嘉泰姆

Gate-Off Linear-Regulator Feedback Input. Connect FBN to the center of ahNv嘉泰姆
resistive voltage-divider between the regulator output and REF to set thehNv嘉泰姆
gate-off linear regulator output voltage. Place the resistive voltage-dividerhNv嘉泰姆
close to the pin.hNv嘉泰姆

28hNv嘉泰姆

DRVNhNv嘉泰姆

DRVNhNv嘉泰姆

DRVNhNv嘉泰姆

Gate-Off Linear-Regulator Base Drive. Open drain of an internal p-channelhNv嘉泰姆
MOSFET. Connect DRVN to the base of an external NPN pass transistor.hNv嘉泰姆

29hNv嘉泰姆

DELhNv嘉泰姆

DELhNv嘉泰姆

DELhNv嘉泰姆

High-Voltage Switch Delay Input. Connect a capacitor from DEL to AGND tohNv嘉泰姆
set the high-voltage switch startup delay.hNv嘉泰姆

30hNv嘉泰姆

CTLhNv嘉泰姆

CTLhNv嘉泰姆

CTLhNv嘉泰姆

High-Voltage Switch Control Input. When CTL is high, the high-voltage switchhNv嘉泰姆
between COM and SRC is on and the high-voltage switch between COM andhNv嘉泰姆
DRN is off. When CTL is low, the high-voltage switch between COM and SRChNv嘉泰姆
is off and the high-voltage switch between COM and DRN is on. CTL ishNv嘉泰姆
inhibited by the undervoltage lockout and when the voltage on DEL is less thanhNv嘉泰姆
1.25V.hNv嘉泰姆

31hNv嘉泰姆

DRNhNv嘉泰姆

DRNhNv嘉泰姆

DRNhNv嘉泰姆

Switch Input. Drain of the internal high-voltage back-to-back P-channelhNv嘉泰姆
MOSFETs connected to COM. Do not allows the voltage on DRN to exceedhNv嘉泰姆
VSRC.hNv嘉泰姆

32hNv嘉泰姆

COMhNv嘉泰姆

COMhNv嘉泰姆

COMhNv嘉泰姆

Internal High-Voltage MOSFET Switch Common Terminal. Do not allow thehNv嘉泰姆
voltage on COM to exceed VSRC.hNv嘉泰姆

六.电路原理图hNv嘉泰姆
七,功能概述hNv嘉泰姆
For all switching power supplies, the layout is an impor-tant step in the design; especially at high peak currents and switching frequencies. There are some general guidelines for layout:hNv嘉泰姆
1.Place the external power components (the input capacitors, output capacitors, boost inductor and output diodes, etc.) in close proximity to the device.Traces to these components should be kept as short and wide as possible to minimize parasitic inductance and resistance.hNv嘉泰姆
2.Place the REF and IN bypass capacitors close to the pins. The ground connection of the IN bypass capacitor should be connected directly to the AGND pin with a wide trace.hNv嘉泰姆
3.Create a power ground (PGND) and a signal ground island and connect at only one point. The power ground consisting of the input and output capacitor grounds, PGND pin, and any charge-pump components. Connect all of these together with short, wide traces or a small ground plane. Maxi-mizing the width of the power ground traces im-proves efficiency and reduces output voltage ripple and noise spikes. The analog ground plane (AGND) consisting of the AGND pin, all the feed-back-divider ground connections, the operational-amplifier divider ground connections, the COMP and DEL capacitor ground connections, and the device’s exposed backside pad. Connect the AGND and PGND islands by connecting the PGND pin directly to the exposed backside pad. Make no other connections between these separate ground planes.hNv嘉泰姆
4.The feedback network should sense the output volt-age directly from the point of load, and be as far away from LX node as possible.hNv嘉泰姆
5.The exposed die plate, underneath the package,should be soldered to an equivalent area of metal on the PCB. This contact area should have mul-tiple via connections to the back of the PCB as well as connections to intermediate PCB layers, if available, to maximize thermal dissipation away from the IC.hNv嘉泰姆
6.To minimize the thermal resistance of the package when soldered to a multi-layer PCB, the amount of copper track and ground plane area connected to the exposed die plate should be maximized and spread out as far as possible from the IC. The bot-tom and top PCB areas especially should be maxi-mized to allow thermal dissipation to the surround-ing air.hNv嘉泰姆
7.Minimize feedback input track lengths to avoid switching noise pick-uphNv嘉泰姆
八,相关产品hNv嘉泰姆

Switching Regulator > Boost ConverterhNv嘉泰姆

 Part_No hNv嘉泰姆

PackagehNv嘉泰姆

Archi-tecture hNv嘉泰姆

Input hNv嘉泰姆

Voltage    hNv嘉泰姆

Max Adj.hNv嘉泰姆

Output hNv嘉泰姆

Voltage hNv嘉泰姆

Switch Current Limit (max) hNv嘉泰姆

Fixed hNv嘉泰姆

Output hNv嘉泰姆

Voltage  hNv嘉泰姆

Switching hNv嘉泰姆

Frequency hNv嘉泰姆

Internal Power   Switch hNv嘉泰姆

Sync. Rectifier hNv嘉泰姆

 

minhNv嘉泰姆

maxhNv嘉泰姆

minhNv嘉泰姆

maxhNv嘉泰姆

(A)hNv嘉泰姆

(V)hNv嘉泰姆

(kHz)hNv嘉泰姆

 

CXSU63133hNv嘉泰姆

SOT89hNv嘉泰姆

VM hNv嘉泰姆

0.9hNv嘉泰姆

5.5hNv嘉泰姆

2.5hNv嘉泰姆

5.5hNv嘉泰姆

0.5hNv嘉泰姆

1.8|2.6|2.8|3hNv嘉泰姆

|3.3|3.8|4.5|5hNv嘉泰姆

-hNv嘉泰姆

NohNv嘉泰姆

YeshNv嘉泰姆

CXSU63134hNv嘉泰姆

MSOP8|TSSOP8hNv嘉泰姆

|SOP8hNv嘉泰姆

VMhNv嘉泰姆

2.5hNv嘉泰姆

5.5hNv嘉泰姆

2.5hNv嘉泰姆

-hNv嘉泰姆

-hNv嘉泰姆

-hNv嘉泰姆

200 ~ 1000hNv嘉泰姆

NohNv嘉泰姆

NohNv嘉泰姆

CXSU63135hNv嘉泰姆

TSSOP8|SOP-8PhNv嘉泰姆

VMhNv嘉泰姆

1hNv嘉泰姆

5.5hNv嘉泰姆

2.5hNv嘉泰姆

5hNv嘉泰姆

1hNv嘉泰姆

2.5|3.3hNv嘉泰姆

300hNv嘉泰姆

YeshNv嘉泰姆

YeshNv嘉泰姆

CXSU63136hNv嘉泰姆

SOP8hNv嘉泰姆

CMhNv嘉泰姆

3hNv嘉泰姆

40hNv嘉泰姆

1.25hNv嘉泰姆

40hNv嘉泰姆

1.5hNv嘉泰姆

-hNv嘉泰姆

33 ~ 100hNv嘉泰姆

YeshNv嘉泰姆

NohNv嘉泰姆

CXSU63137hNv嘉泰姆

TQFN5x5-32hNv嘉泰姆

CMhNv嘉泰姆

2.5hNv嘉泰姆

6.5hNv嘉泰姆

2.5hNv嘉泰姆

18hNv嘉泰姆

3hNv嘉泰姆

NohNv嘉泰姆

1200hNv嘉泰姆

YeshNv嘉泰姆

NohNv嘉泰姆

CXSU63138hNv嘉泰姆

TSOT23-5hNv嘉泰姆

TDFN2x2-6hNv嘉泰姆

CMhNv嘉泰姆

2.5hNv嘉泰姆

6hNv嘉泰姆

2.5hNv嘉泰姆

20hNv嘉泰姆

2hNv嘉泰姆

-hNv嘉泰姆

1500hNv嘉泰姆

YeshNv嘉泰姆

NohNv嘉泰姆

CXSU63139hNv嘉泰姆

TQFN4x4-6hNv嘉泰姆

TDFN3x3-12hNv嘉泰姆

CMhNv嘉泰姆

1.8hNv嘉泰姆

5.5hNv嘉泰姆

2.7hNv嘉泰姆

5.5hNv嘉泰姆

5hNv嘉泰姆

-hNv嘉泰姆

1.2hNv嘉泰姆

YeshNv嘉泰姆

YeshNv嘉泰姆

CXSU63140hNv嘉泰姆

SOT23-5hNv嘉泰姆

CMhNv嘉泰姆

2.5hNv嘉泰姆

6hNv嘉泰姆

2.5hNv嘉泰姆

32hNv嘉泰姆

1hNv嘉泰姆

-hNv嘉泰姆

1000hNv嘉泰姆

YeshNv嘉泰姆

NohNv嘉泰姆

CXSU63141hNv嘉泰姆

TSOT-23-6 hNv嘉泰姆

TDFN2x2-8hNv嘉泰姆

CMhNv嘉泰姆

1.2hNv嘉泰姆

5.5hNv嘉泰姆

1.8hNv嘉泰姆

5.5hNv嘉泰姆

1.2hNv嘉泰姆

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YeshNv嘉泰姆

YeshNv嘉泰姆

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