CXSU63137

CXSU63137集成了一个高性能升压转换器、两个线性调节器控制器、一个高压开关和一个(CXSU63137)、三个(CXSU63137)或五个(CXSU63137)大电流运算放大器,用于TFT-LCD应用。主升压调节器是电流模式、固定频率的PWM开关调节器。1.2兆赫的开关频率允许使用低剖面感应器和陶瓷电容器,以最小化液晶面板设计的厚度

2.6V至6.5V输入电源VGON和VGOFF的线性调节器控制器CXSU63137电流模式升压调节器大电流运算放大器

产品手册

产品订购

产品简介

目录aIU嘉泰姆

1.产品概述                       2.产品特点aIU嘉泰姆
3.应用范围                       4.下载产品资料PDF文档 aIU嘉泰姆
5.产品封装图                     6.电路原理图                   aIU嘉泰姆
7.功能概述                        8.相关产品aIU嘉泰姆

一,产品概述(General Description)         aIU嘉泰姆


           The CXSU63137 integrates with a high-performance step-up converter, two linear-regulator controllers, a high voltage switch and one (CXSU63137), three (CXSU63137) or five (CXSU63137) high current operational amplifiers for TFT-LCD applications.The main step-up regulator is a current-mode, fixed-fre-quency PWM switching regulator. The 1.2MHz switching frequency allows the usage of low-profile inductors and ceramic capacitors to minimize the thickness of LCD panel designs.aIU嘉泰姆
      The linear-regulator controllers used external transistors provide regulated the gate-driver of TFT-LCD VGON and VGOFF supplies.aIU嘉泰姆
The amplifiers are ideal for VCOM and VGAMMA applications, withaIU嘉泰姆
150m A peak output current drive, 10MHz bandwidth, and 13V/μs slewaIU嘉泰姆
rate. All inputs and outputs are rail-to-rail.aIU嘉泰姆
     The CXSU63137/1/2 is available in a tiny 5mm x 5mm 32-pin QFN package (TQFN5x5-32).aIU嘉泰姆
二.产品特点(Features)aIU嘉泰姆


· 2.6V to 6.5V Input Supply Range aIU嘉泰姆

· Current-Mode Step-Up Regulator aIU嘉泰姆

 - Fast Transient Response aIU嘉泰姆

 - 1.2MHz Fixed Operating Frequency aIU嘉泰姆

· ±1.5% High-Accuracy Output Voltage aIU嘉泰姆

· 3A, 20V, 0.25W Internal N-Channel MOSFET aIU嘉泰姆

· High Efficiency aIU嘉泰姆

· Low Quiescent Current (0.6mA Typical) aIU嘉泰姆

· Linear-Regulator Controllers for VGON and VGOFF aIU嘉泰姆

· High-performance Operational Amplifiers aIU嘉泰姆

 - ±150mA Output Short-Circuit CurrentaIU嘉泰姆

 - 13V/ms Slew Rate - 10MHz, -3dB Bandwidth aIU嘉泰姆

 - Rail-to-Rail Inputs/Outputs aIU嘉泰姆

· Fault-Delay Timer and Fault Latch for All Regulator Outputs aIU嘉泰姆

· Over-Temperature Protection aIU嘉泰姆

· Available in Compact 32-pin 5mmx5mm Thin QFN Package (TQFN5x5-32) aIU嘉泰姆

· Lead Free Available (RoHS Compliant)aIU嘉泰姆

三,应用范围 (Applications)aIU嘉泰姆


    TFT LCD Displays for MonitorsaIU嘉泰姆
   TFT LCD Displays for Notebook ComputersaIU嘉泰姆
   Automotive DisplaysaIU嘉泰姆
四.下载产品资料PDF文档 aIU嘉泰姆


需要详细的PDF规格书请扫一扫微信联系我们,还可以获得免费样品以及技术支持aIU嘉泰姆

 QQ截图20160419174301.jpgaIU嘉泰姆

五,产品封装图 (Package)aIU嘉泰姆


blob.pngaIU嘉泰姆
blob.pngPin Function DescriptionaIU嘉泰姆

PinaIU嘉泰姆

NameaIU嘉泰姆

Function DescriptionaIU嘉泰姆

CXSU63137aIU嘉泰姆

CXSU63137-1aIU嘉泰姆

CXSU63137-2aIU嘉泰姆

1aIU嘉泰姆

SRCaIU嘉泰姆

SRCaIU嘉泰姆

SRCaIU嘉泰姆

Switch Input. Source of the internal high-voltage P-channel MOSFET. BypassaIU嘉泰姆
SRC to PGND with a minimum of 0.1μF capacitor closed to the pins.aIU嘉泰姆

2aIU嘉泰姆

REFaIU嘉泰姆

REFaIU嘉泰姆

REFaIU嘉泰姆

Reference voltage output. Bypass REF to AGND with a minimum ofaIU嘉泰姆
0.22μFcapacitor closed to the pins.aIU嘉泰姆

3aIU嘉泰姆

AGNDaIU嘉泰姆

AGNDaIU嘉泰姆

AGNDaIU嘉泰姆

Analog Ground for Step-Up Regulator and Linear Regulators. Connect toaIU嘉泰姆
power ground (PGND) underneath the IC.aIU嘉泰姆

4aIU嘉泰姆

PGNDaIU嘉泰姆

PGNDaIU嘉泰姆

PGNDaIU嘉泰姆

Power Ground for Step-Up Regulator. PGND is the source of the main step-upaIU嘉泰姆
n-channel power MOSFET. Connect PGND to the ground terminals of outputaIU嘉泰姆
capacitors through a short, wide PC board trace. Connect to analog groundaIU嘉泰姆
(AGND) underneath the IC.aIU嘉泰姆

5aIU嘉泰姆

OUT1aIU嘉泰姆

OUT1aIU嘉泰姆

OUT1aIU嘉泰姆

Output of Operational-Amplifier 1aIU嘉泰姆

6aIU嘉泰姆

NEG1aIU嘉泰姆

NEG1aIU嘉泰姆

NEG1aIU嘉泰姆

Inverting Input of Operational-Amplifier 1aIU嘉泰姆

7aIU嘉泰姆

POS1aIU嘉泰姆

POS1aIU嘉泰姆

POS1aIU嘉泰姆

Non-inverting Input of Operational-Amplifier 1aIU嘉泰姆

8aIU嘉泰姆

NCaIU嘉泰姆

OUT2aIU嘉泰姆

OUT2aIU嘉泰姆

Output of Operational-Amplifier 2 of CXSU63137/CXSU63137. No internalaIU嘉泰姆
connected of CXSU63137.aIU嘉泰姆

9aIU嘉泰姆

NCaIU嘉泰姆

NEG2aIU嘉泰姆

NEG2aIU嘉泰姆

Inverting Input of Operational-Amplifier 2 of CXSU63137/CXSU63137. No internalaIU嘉泰姆
connected of CXSU63137.aIU嘉泰姆

10aIU嘉泰姆

ICaIU嘉泰姆

POS2aIU嘉泰姆

POS2aIU嘉泰姆

Non-inverting Input of Operational-Amplifier 2 of CXSU63137/CXSU63137. InternalaIU嘉泰姆
connected to GND of CXSU63137aIU嘉泰姆

11aIU嘉泰姆

BGNDaIU嘉泰姆

BGNDaIU嘉泰姆

BGNDaIU嘉泰姆

Analog Ground for Operational Amplifiers. Connect to power ground (PGND)aIU嘉泰姆
underneath the IC.aIU嘉泰姆

12aIU嘉泰姆

NCaIU嘉泰姆

NCaIU嘉泰姆

POS3aIU嘉泰姆

Non-inverting Input of Operational-Amplifier 3 of CXSU63137. No internalaIU嘉泰姆
connected of CXSU63137/CXSU63137.aIU嘉泰姆

13aIU嘉泰姆

NCaIU嘉泰姆

NCaIU嘉泰姆

OUT3aIU嘉泰姆

Output of Operational-Amplifier 3 of CXSU63137. No internal connected ofCXSU63137/CXSU63137.aIU嘉泰姆

14aIU嘉泰姆

SUPaIU嘉泰姆

SUPaIU嘉泰姆

SUPaIU嘉泰姆

Power Input of Operational Amplifiers. Typically connected to VMAIN. BypassaIU嘉泰姆
SUP to BGND with a 0.1μF capacitor.aIU嘉泰姆

15aIU嘉泰姆

NCaIU嘉泰姆

POS3aIU嘉泰姆

POS4aIU嘉泰姆

Non-inverting Input of Operational-Amplifier 4 of CXSU63137. Non-invertingaIU嘉泰姆
Input of Operational-Amplifier 3 of CXSU63137. No internal connected ofCXSU63137.aIU嘉泰姆

16aIU嘉泰姆

NCaIU嘉泰姆

NEG3aIU嘉泰姆

NEG4aIU嘉泰姆

Inverting Input of Operational-Amplifier 4 of CXSU63137. Inverting Input ofaIU嘉泰姆
Operational-Amplifier 3 of CXSU63137. No internal connected of CXSU63137.aIU嘉泰姆

17aIU嘉泰姆

NCaIU嘉泰姆

OUT3aIU嘉泰姆

OUT4aIU嘉泰姆

Output of Operational-Amplifier 4 of CXSU63137. Output ofaIU嘉泰姆
Operational-Amplifier 3 of CXSU63137. No internal connected of CXSU63137.aIU嘉泰姆

18aIU嘉泰姆

ICaIU嘉泰姆

ICaIU嘉泰姆

POS5aIU嘉泰姆

Non-inverting Input of Operational-Amplifier 5 of CXSU63137. Internal connectedaIU嘉泰姆
to GND of CXSU63137/CXSU63137.aIU嘉泰姆

19aIU嘉泰姆

NCaIU嘉泰姆

NCaIU嘉泰姆

NEG5aIU嘉泰姆

Inverting Input of Operational-Amplifier 5 of CXSU63137. No internal connectedaIU嘉泰姆
of CXSU63137/CXSU63137.aIU嘉泰姆

20aIU嘉泰姆

NCaIU嘉泰姆

NCaIU嘉泰姆

OUT5aIU嘉泰姆

Output of Operational-Amplifier 5 of CXSU63137. No internal connected ofCXSU63137/CXSU63137.aIU嘉泰姆

21aIU嘉泰姆

LXaIU嘉泰姆

LXaIU嘉泰姆

LXaIU嘉泰姆

N-Channel Power MOSFET Drain and Switching Node. Connect the inductoraIU嘉泰姆
and Schottky diode to LX and minimize the trace area for lowest EMI.aIU嘉泰姆

22aIU嘉泰姆

INaIU嘉泰姆

INaIU嘉泰姆

INaIU嘉泰姆

Supply Voltage Input. Bypass IN to AGND with a 0.1μF capacitor. IN can rangeaIU嘉泰姆
from 2.6V to 6.5V.aIU嘉泰姆

23aIU嘉泰姆

FBaIU嘉泰姆

FBaIU嘉泰姆

FBaIU嘉泰姆

Step-Up Regulator Feedback Input. Connect a resistive voltage-divider fromaIU嘉泰姆
the output (VMAIN) to FB to analog ground (AGND). Place the divider withinaIU嘉泰姆
5mm of FB.aIU嘉泰姆

24aIU嘉泰姆

COMPaIU嘉泰姆

COMPaIU嘉泰姆

COMPaIU嘉泰姆

Step-Up Regulator Error-Amplifier Compensation Point. Connect a series RCaIU嘉泰姆
from COMP to AGND.aIU嘉泰姆

PinFunction DescriptionaIU嘉泰姆

PinaIU嘉泰姆

NameaIU嘉泰姆

Function DescriptionaIU嘉泰姆

CXSU63137aIU嘉泰姆

CXSU63137-1aIU嘉泰姆

CXSU63137-2aIU嘉泰姆

24aIU嘉泰姆

COMPaIU嘉泰姆

COMPaIU嘉泰姆

COMPaIU嘉泰姆

Step-Up Regulator Error-Amplifier Compensation Point. Connect a series RCaIU嘉泰姆
from COMP to AGND.aIU嘉泰姆

25aIU嘉泰姆

FBPaIU嘉泰姆

FBPaIU嘉泰姆

FBPaIU嘉泰姆

Gate-On Linear-Regulator Feedback Input. Connect FBP to the center of aaIU嘉泰姆
resistive voltage-divider between the regulator output and AGND to set theaIU嘉泰姆
gate-on linear regulator output voltage. Place the resistive voltage-divideraIU嘉泰姆
close to the pin.aIU嘉泰姆

26aIU嘉泰姆

DRVPaIU嘉泰姆

DRVPaIU嘉泰姆

DRVPaIU嘉泰姆

Gate-On Linear-Regulator Base Drive. Open drain of an internal n-channelaIU嘉泰姆
MOSFET. Connect DRVP to the base of an external PNP pass transistor.aIU嘉泰姆

27aIU嘉泰姆

FBNaIU嘉泰姆

FBNaIU嘉泰姆

FBNaIU嘉泰姆

Gate-Off Linear-Regulator Feedback Input. Connect FBN to the center of aaIU嘉泰姆
resistive voltage-divider between the regulator output and REF to set theaIU嘉泰姆
gate-off linear regulator output voltage. Place the resistive voltage-divideraIU嘉泰姆
close to the pin.aIU嘉泰姆

28aIU嘉泰姆

DRVNaIU嘉泰姆

DRVNaIU嘉泰姆

DRVNaIU嘉泰姆

Gate-Off Linear-Regulator Base Drive. Open drain of an internal p-channelaIU嘉泰姆
MOSFET. Connect DRVN to the base of an external NPN pass transistor.aIU嘉泰姆

29aIU嘉泰姆

DELaIU嘉泰姆

DELaIU嘉泰姆

DELaIU嘉泰姆

High-Voltage Switch Delay Input. Connect a capacitor from DEL to AGND toaIU嘉泰姆
set the high-voltage switch startup delay.aIU嘉泰姆

30aIU嘉泰姆

CTLaIU嘉泰姆

CTLaIU嘉泰姆

CTLaIU嘉泰姆

High-Voltage Switch Control Input. When CTL is high, the high-voltage switchaIU嘉泰姆
between COM and SRC is on and the high-voltage switch between COM andaIU嘉泰姆
DRN is off. When CTL is low, the high-voltage switch between COM and SRCaIU嘉泰姆
is off and the high-voltage switch between COM and DRN is on. CTL isaIU嘉泰姆
inhibited by the undervoltage lockout and when the voltage on DEL is less thanaIU嘉泰姆
1.25V.aIU嘉泰姆

31aIU嘉泰姆

DRNaIU嘉泰姆

DRNaIU嘉泰姆

DRNaIU嘉泰姆

Switch Input. Drain of the internal high-voltage back-to-back P-channelaIU嘉泰姆
MOSFETs connected to COM. Do not allows the voltage on DRN to exceedaIU嘉泰姆
VSRC.aIU嘉泰姆

32aIU嘉泰姆

COMaIU嘉泰姆

COMaIU嘉泰姆

COMaIU嘉泰姆

Internal High-Voltage MOSFET Switch Common Terminal. Do not allow theaIU嘉泰姆
voltage on COM to exceed VSRC.aIU嘉泰姆

六.电路原理图aIU嘉泰姆
七,功能概述aIU嘉泰姆
For all switching power supplies, the layout is an impor-tant step in the design; especially at high peak currents and switching frequencies. There are some general guidelines for layout:aIU嘉泰姆
1.Place the external power components (the input capacitors, output capacitors, boost inductor and output diodes, etc.) in close proximity to the device.Traces to these components should be kept as short and wide as possible to minimize parasitic inductance and resistance.aIU嘉泰姆
2.Place the REF and IN bypass capacitors close to the pins. The ground connection of the IN bypass capacitor should be connected directly to the AGND pin with a wide trace.aIU嘉泰姆
3.Create a power ground (PGND) and a signal ground island and connect at only one point. The power ground consisting of the input and output capacitor grounds, PGND pin, and any charge-pump components. Connect all of these together with short, wide traces or a small ground plane. Maxi-mizing the width of the power ground traces im-proves efficiency and reduces output voltage ripple and noise spikes. The analog ground plane (AGND) consisting of the AGND pin, all the feed-back-divider ground connections, the operational-amplifier divider ground connections, the COMP and DEL capacitor ground connections, and the device’s exposed backside pad. Connect the AGND and PGND islands by connecting the PGND pin directly to the exposed backside pad. Make no other connections between these separate ground planes.aIU嘉泰姆
4.The feedback network should sense the output volt-age directly from the point of load, and be as far away from LX node as possible.aIU嘉泰姆
5.The exposed die plate, underneath the package,should be soldered to an equivalent area of metal on the PCB. This contact area should have mul-tiple via connections to the back of the PCB as well as connections to intermediate PCB layers, if available, to maximize thermal dissipation away from the IC.aIU嘉泰姆
6.To minimize the thermal resistance of the package when soldered to a multi-layer PCB, the amount of copper track and ground plane area connected to the exposed die plate should be maximized and spread out as far as possible from the IC. The bot-tom and top PCB areas especially should be maxi-mized to allow thermal dissipation to the surround-ing air.aIU嘉泰姆
7.Minimize feedback input track lengths to avoid switching noise pick-upaIU嘉泰姆
八,相关产品aIU嘉泰姆

Switching Regulator > Boost ConverteraIU嘉泰姆

 Part_No aIU嘉泰姆

PackageaIU嘉泰姆

Archi-tecture aIU嘉泰姆

Input aIU嘉泰姆

Voltage    aIU嘉泰姆

Max Adj.aIU嘉泰姆

Output aIU嘉泰姆

Voltage aIU嘉泰姆

Switch Current Limit (max) aIU嘉泰姆

Fixed aIU嘉泰姆

Output aIU嘉泰姆

Voltage  aIU嘉泰姆

Switching aIU嘉泰姆

Frequency aIU嘉泰姆

Internal Power   Switch aIU嘉泰姆

Sync. Rectifier aIU嘉泰姆

 

minaIU嘉泰姆

maxaIU嘉泰姆

minaIU嘉泰姆

maxaIU嘉泰姆

(A)aIU嘉泰姆

(V)aIU嘉泰姆

(kHz)aIU嘉泰姆

 

CXSU63133aIU嘉泰姆

SOT89aIU嘉泰姆

VM aIU嘉泰姆

0.9aIU嘉泰姆

5.5aIU嘉泰姆

2.5aIU嘉泰姆

5.5aIU嘉泰姆

0.5aIU嘉泰姆

1.8|2.6|2.8|3aIU嘉泰姆

|3.3|3.8|4.5|5aIU嘉泰姆

-aIU嘉泰姆

NoaIU嘉泰姆

YesaIU嘉泰姆

CXSU63134aIU嘉泰姆

MSOP8|TSSOP8aIU嘉泰姆

|SOP8aIU嘉泰姆

VMaIU嘉泰姆

2.5aIU嘉泰姆

5.5aIU嘉泰姆

2.5aIU嘉泰姆

-aIU嘉泰姆

-aIU嘉泰姆

-aIU嘉泰姆

200 ~ 1000aIU嘉泰姆

NoaIU嘉泰姆

NoaIU嘉泰姆

CXSU63135aIU嘉泰姆

TSSOP8|SOP-8PaIU嘉泰姆

VMaIU嘉泰姆

1aIU嘉泰姆

5.5aIU嘉泰姆

2.5aIU嘉泰姆

5aIU嘉泰姆

1aIU嘉泰姆

2.5|3.3aIU嘉泰姆

300aIU嘉泰姆

YesaIU嘉泰姆

YesaIU嘉泰姆

CXSU63136aIU嘉泰姆

SOP8aIU嘉泰姆

CMaIU嘉泰姆

3aIU嘉泰姆

40aIU嘉泰姆

1.25aIU嘉泰姆

40aIU嘉泰姆

1.5aIU嘉泰姆

-aIU嘉泰姆

33 ~ 100aIU嘉泰姆

YesaIU嘉泰姆

NoaIU嘉泰姆

CXSU63137aIU嘉泰姆

TQFN5x5-32aIU嘉泰姆

CMaIU嘉泰姆

2.5aIU嘉泰姆

6.5aIU嘉泰姆

2.5aIU嘉泰姆

18aIU嘉泰姆

3aIU嘉泰姆

NoaIU嘉泰姆

1200aIU嘉泰姆

YesaIU嘉泰姆

NoaIU嘉泰姆

CXSU63138aIU嘉泰姆

TSOT23-5aIU嘉泰姆

TDFN2x2-6aIU嘉泰姆

CMaIU嘉泰姆

2.5aIU嘉泰姆

6aIU嘉泰姆

2.5aIU嘉泰姆

20aIU嘉泰姆

2aIU嘉泰姆

-aIU嘉泰姆

1500aIU嘉泰姆

YesaIU嘉泰姆

NoaIU嘉泰姆

CXSU63139aIU嘉泰姆

TQFN4x4-6aIU嘉泰姆

TDFN3x3-12aIU嘉泰姆

CMaIU嘉泰姆

1.8aIU嘉泰姆

5.5aIU嘉泰姆

2.7aIU嘉泰姆

5.5aIU嘉泰姆

5aIU嘉泰姆

-aIU嘉泰姆

1.2aIU嘉泰姆

YesaIU嘉泰姆

YesaIU嘉泰姆

CXSU63140aIU嘉泰姆

SOT23-5aIU嘉泰姆

CMaIU嘉泰姆

2.5aIU嘉泰姆

6aIU嘉泰姆

2.5aIU嘉泰姆

32aIU嘉泰姆

1aIU嘉泰姆

-aIU嘉泰姆

1000aIU嘉泰姆

YesaIU嘉泰姆

NoaIU嘉泰姆

CXSU63141aIU嘉泰姆

TSOT-23-6 aIU嘉泰姆

TDFN2x2-8aIU嘉泰姆

CMaIU嘉泰姆

1.2aIU嘉泰姆

5.5aIU嘉泰姆

1.8aIU嘉泰姆

5.5aIU嘉泰姆

1.2aIU嘉泰姆

-aIU嘉泰姆

1.2aIU嘉泰姆

YesaIU嘉泰姆

YesaIU嘉泰姆

 aIU嘉泰姆

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