CXSD62104

CXSD62104集成了双降压、恒定时间、同步PWM控制器(为每个通道驱动双N通道mosfet)和
两个低损耗稳压器以及各种保护装置集成到一个芯片中。PWM控制器降低电池的高电压以产生NB的低电压应用。PWM1和PWM2的输出可以从2V调整到5.5V通过设置一个从VOUTx到GND的电阻分压器。线性调节器为备用电源提供5V和3.3V输出

CXSD62104双降压恒时同步的PWM控制器两个低损耗稳压器PWM1和PWM2的输出可以从2V调整到5.5V

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产品简介

目录pOd嘉泰姆

1.产品概述                       2.产品特点pOd嘉泰姆
3.应用范围                       4.下载产品资料PDF文档 pOd嘉泰姆
5.产品封装图                     6.电路原理图                   pOd嘉泰姆
7.功能概述                        8.相关产品pOd嘉泰姆

一,产品概述(General Description)         pOd嘉泰姆

        The CXSD62104  integrates dual step-down, constant-ontime, synchronouspOd嘉泰姆

PWM controllers (that drives dual N-channel MOSFETs for each channel) andpOd嘉泰姆
two low drop-out regulators as well as various protections into a chip.The PWMpOd嘉泰姆
controllers step down high voltage of a battery to generate low-voltage for NBpOd嘉泰姆
applications. The output of PWM1 and PWM2 can be adjusted from 2V to 5.5VpOd嘉泰姆
by setting a resistive voltage-divider from VOUTx to GND.The linear regulatorspOd嘉泰姆
provide 5V and 3.3V output for standby power supply. The linear regulatorspOd嘉泰姆

provide up to 100mA output current. When the PWMx output voltage is higher pOd嘉泰姆

than LDOx bypass threshold, the related LDOx regulator is shut off and its pOd嘉泰姆

output is connected to VOUTx by internal switchover MOSFET. It can save power dissipation.pOd嘉泰姆
     The CXSD62104 provides excellent transient response and accurate DC pOd嘉泰姆

output voltage in either PFM or PWM Mode.In Pulse-Frequency Mode (PFM), pOd嘉泰姆

the CXSD62104 provides very high efficiency over light to heavy loads with pOd嘉泰姆

loading-modulated switching frequencies. The Forced-PWM mode works nearly pOd嘉泰姆

at constant frequency for low-noise requirements. The unique ultrasonic modepOd嘉泰姆

 maintains the switching frequency above 25KHz, which eliminates noise in audio applications.pOd嘉泰姆

     The CXSD62104 is equipped with accurate sourcing cur-rent-limit, outputpOd嘉泰姆

under-voltage and output over-voltage protections, being perfect for NB pOd嘉泰姆

applications. A 1.7ms (typ.) digital soft-start can reduce the start-up current. pOd嘉泰姆

A soft-stop function actively discharges the output capaci-tors by the discharge pOd嘉泰姆

device. The CXSD62104 has individual enable controls for PWM channels and pOd嘉泰姆

LDOs. Pulling both ENPWM pin and ENLDO pin low shuts down the whole chippOd嘉泰姆

with low quiescent current close to zero.pOd嘉泰姆
      The CXSD62104 is available in a TQFN4x4-24A package.pOd嘉泰姆
二.产品特点(Features)pOd嘉泰姆
Wide Input Voltage Range from 6V to 25VpOd嘉泰姆
Provide 4 Independent Outputs with ±1.5% Accu-pOd嘉泰姆
racy Over-TemperaturepOd嘉泰姆
- PWM1 Controller with Adjustable (2V to 5.5V) Out-putpOd嘉泰姆
PWM2 Controller with Adjustable (2V to 5.5V) Out-putpOd嘉泰姆
100mA Low Dropout Regulator (LDO5) with Fixed 5V OutputpOd嘉泰姆
100mA Low Dropout Regulator (LDO3) with Fixed 3.3V OutputpOd嘉泰姆
Excellent Line/Load Regulations about ±1.5% Over-Temperature RangepOd嘉泰姆
±1%, (±1.5%, 50μA) 2.0V Reference Voltage OutputpOd嘉泰姆
Built-In POR Control Scheme ImplementedpOd嘉泰姆
Selectable Forced-PWM or Automatic PFM/PWMpOd嘉泰姆
(with Selectable Ultrasonic Operation)pOd嘉泰姆
Constant-On-Time Control Scheme with FrequencypOd嘉泰姆
Compensation for PWM ModepOd嘉泰姆
Selectable Switching Frequency in PWM ModepOd嘉泰姆
Built-in Digital Soft-Start for PWM Outputs and Soft-pOd嘉泰姆
Stop for PWM Outputs and LDO OutputspOd嘉泰姆
Integrated Bootstrap Forward P-CH MOSFETpOd嘉泰姆
High Efficiency over Light to Full Load Range (PWMs)pOd嘉泰姆
Built-in Power Good Indicators (PWMs)pOd嘉泰姆
Independent Enable Inputs (PWMs, LDO)pOd嘉泰姆

70% Under-Voltage and 125% Over-Voltage Protec-tions (PWM)pOd嘉泰姆

Adjustable Current-Limit Protection (PWMs)pOd嘉泰姆
- Using Sense Low-Side MOSFET’s RDS(ON)pOd嘉泰姆
Over-Temperature ProtectionpOd嘉泰姆
4mmx4mm Thin QFN-24 (TQFN4x4-24A) packagepOd嘉泰姆
Lead Free and Green Device Available (RoHS Compliant)
pOd嘉泰姆

三,应用范围 (Applications)pOd嘉泰姆

Notebook and Sub-Notebook ComputerspOd嘉泰姆

Portable DevicespOd嘉泰姆
DDR1, DDR2, and DDR3 Power SuppliespOd嘉泰姆
3-Cell and 4-Cell Li+ Battery-Powered DevicespOd嘉泰姆
Graphic CardspOd嘉泰姆
Game ConsolespOd嘉泰姆
Telecommunications
pOd嘉泰姆

四.下载产品资料PDF文档 pOd嘉泰姆

需要详细的PDF规格书请扫一扫微信联系我们,还可以获得免费样品以及技术支持pOd嘉泰姆

 QQ截图20160419174301.jpgpOd嘉泰姆

五,产品封装图 (Package)pOd嘉泰姆


blob.pngblob.pngpOd嘉泰姆

六.电路原理图pOd嘉泰姆


blob.pngpOd嘉泰姆

七,功能概述pOd嘉泰姆


Input Capacitor SelectionpOd嘉泰姆
The input capacitor is chosen based on the voltage rating and the RMS current rating. For reliable operation, selectpOd嘉泰姆
the capacitor voltage rating to be at least 1.3 times higher than the maximum input voltage. The maximum RMSpOd嘉泰姆
current rating requirement is approximately IOUT/2, where IOUT is the load current. During power up, the input capaci-tors have to handle large amount of surge current. In low-duty notebook appliactions, ceramic capacitors arepOd嘉泰姆
remmended. The capacitors must be connected between the drain of high-side MOSFET and the source of low-pOd嘉泰姆
side MOSFET with very low-impeadance PCB layout. pOd嘉泰姆
MOSFET SelectionpOd嘉泰姆
The application for a notebook battery with a maximum volt-age of 24V, at least a minimum 30V MOSFETs shouldpOd嘉泰姆
be used. The design has to trade off the gate charge with the RDS(ON) of the MOSFET:pOd嘉泰姆
· For the low-side MOSFET, before it is turned on, the body diode has been conducted. The low-side MOSFETpOd嘉泰姆
driver will not charge the miller capacitor of this MOSFET.pOd嘉泰姆
In the turning off process of the low-side MOSFET,the load current will shift to the body diode first. ThepOd嘉泰姆
high dv/dt of the phase node voltage will charge the miller capacitor through the low-side MOSFET driverpOd嘉泰姆
sinking current path. This results in much less switching loss of the low-side MOSFETs. The dutypOd嘉泰姆
cycle is often very small in high battery voltage applications, and the low-side MOSFET will con-pOd嘉泰姆
duct most of the switching cycle; therefore, the less the RDS(ON) of the low-side MOSFET, the less the powerpOd嘉泰姆
loss. The gate charge for this MOSFET is usually a secondary consideration. The high-side MOSFETpOd嘉泰姆
does not have this zero voltage switching condition, and because it conducts for less timepOd嘉泰姆
compared to the low-side MOSFET, the switching loss tends to be dominant. Priority should be givenpOd嘉泰姆
to the MOSFETs with less gate charge, so that both the gate driver loss and switching loss will be minimized.pOd嘉泰姆
The selection of the N-channel power MOSFETs are de-termined by the RDS(ON), reversing transfer capacitancepOd嘉泰姆
(CRSS) and maximum output current requirement. The losses in the MOSFETs have two components: conduc-pOd嘉泰姆
tion loss and transition loss. For the high-side and low-side MOSFETs, the losses are approximately given bypOd嘉泰姆
the following equations:pOd嘉泰姆
Layout ConsiderationpOd嘉泰姆
In any high switching frequency converter, a correct layout is important to ensure proper operation of the regulator.pOd嘉泰姆
With power devices switching at higher frequency, the resulting current transient will cause voltage spike acrosspOd嘉泰姆
the interconnecting impedance and parasitic circuit elements. As an example, consider the turn-off transitionpOd嘉泰姆
of the PWM MOSFET. Before turn-off condition, the MOSFET is carrying the full load current. During turn-off,pOd嘉泰姆
current stops flowing in the MOSFET and is freewheeling by the lower MOSFET and parasitic diode. Any parasiticpOd嘉泰姆
inductance of the circuit generates a large voltage spike during the switching interval. In general, using short andpOd嘉泰姆
wide printed circuit traces should minimize interconnect-ing impedances and the magnitude of voltage spike. AndpOd嘉泰姆
signal and power grounds are to be kept separating and finally combined to use the ground plane construction orpOd嘉泰姆

single point grounding. The best tie-point between the signal ground and the power ground is at the negativepOd嘉泰姆
side of the output capacitor on each channel, where there is less noise. Noisy traces beneath the IC are notpOd嘉泰姆
recommended. Below is a checklist for your layout:pOd嘉泰姆
Layout Consideration (Cont.)pOd嘉泰姆
Keep the switching nodes (UGATEx, LGATEx, BOOTx,and PHASEx) away from sensitive small signal nodespOd嘉泰姆
(REF, ILIMx, and FBx) since these nodes are fast mov-ing signals. Therefore, keep traces to these nodes aspOd嘉泰姆
short as possible and there should be no other weak signal traces in parallel with theses traces on any layer.pOd嘉泰姆

Minimizing the impedance with wide layout plane be-tween the two pads reduces the voltage bounce ofpOd嘉泰姆

CXSD62104pOd嘉泰姆

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VMpOd嘉泰姆

1pOd嘉泰姆

1pOd嘉泰姆

25pOd嘉泰姆

4pOd嘉泰姆

13.2pOd嘉泰姆

0.8pOd嘉泰姆

5~12pOd嘉泰姆

2000pOd嘉泰姆

CXSD6298pOd嘉泰姆

TDFN3x3-10pOd嘉泰姆

COTpOd嘉泰姆

1pOd嘉泰姆

1pOd嘉泰姆

25pOd嘉泰姆

4.5pOd嘉泰姆

25pOd嘉泰姆

0.6pOd嘉泰姆

5~12pOd嘉泰姆

80pOd嘉泰姆

CXSD6299|ApOd嘉泰姆

SOP-8PpOd嘉泰姆

VMpOd嘉泰姆

1pOd嘉泰姆

1pOd嘉泰姆

25pOd嘉泰姆

4.5pOd嘉泰姆

13.2pOd嘉泰姆

0.8pOd嘉泰姆

5~12pOd嘉泰姆

16000pOd嘉泰姆

CXSD62100pOd嘉泰姆

TQFN3x3-10pOd嘉泰姆

VMpOd嘉泰姆

1pOd嘉泰姆

1pOd嘉泰姆

25pOd嘉泰姆

4.5pOd嘉泰姆

13.2pOd嘉泰姆

0.6pOd嘉泰姆

5~12pOd嘉泰姆

2500pOd嘉泰姆

CXSD62101|LpOd嘉泰姆

TDFN3x3-10pOd嘉泰姆

COTpOd嘉泰姆

1pOd嘉泰姆

1pOd嘉泰姆

30pOd嘉泰姆

3pOd嘉泰姆

25pOd嘉泰姆

0.8pOd嘉泰姆

5~12pOd嘉泰姆

2000pOd嘉泰姆

CXSD62102pOd嘉泰姆

TQFN3x3-16pOd嘉泰姆

COTpOd嘉泰姆

1pOd嘉泰姆

1pOd嘉泰姆

30pOd嘉泰姆

1.8pOd嘉泰姆

28pOd嘉泰姆

0.6pOd嘉泰姆

5pOd嘉泰姆

600pOd嘉泰姆

CXSD62102ApOd嘉泰姆

TQFN 3x3 16pOd嘉泰姆

COTpOd嘉泰姆

1pOd嘉泰姆

1pOd嘉泰姆

30pOd嘉泰姆

1.8pOd嘉泰姆

28pOd嘉泰姆

0.6pOd嘉泰姆

5pOd嘉泰姆

600pOd嘉泰姆

CXSD62103pOd嘉泰姆

QFN4x4-24pOd嘉泰姆

VMpOd嘉泰姆

2pOd嘉泰姆

1pOd嘉泰姆

50pOd嘉泰姆

4.5pOd嘉泰姆

13.2pOd嘉泰姆

0.6pOd嘉泰姆

5~12pOd嘉泰姆

5000pOd嘉泰姆

CXSD62104pOd嘉泰姆

TQFN4x4-24pOd嘉泰姆

COTpOd嘉泰姆

1pOd嘉泰姆

2pOd嘉泰姆

15pOd嘉泰姆

6pOd嘉泰姆

25pOd嘉泰姆

2pOd嘉泰姆

NpOd嘉泰姆

550pOd嘉泰姆

CXSD62105pOd嘉泰姆

TQFN4x4-24pOd嘉泰姆

COTpOd嘉泰姆

1pOd嘉泰姆

2pOd嘉泰姆

15pOd嘉泰姆

6pOd嘉泰姆

25pOd嘉泰姆

2pOd嘉泰姆

NpOd嘉泰姆

550pOd嘉泰姆

CXSD62106|ApOd嘉泰姆

TQFN4x4-4pOd嘉泰姆

TQFN3x3-20pOd嘉泰姆

COTpOd嘉泰姆

1pOd嘉泰姆

2pOd嘉泰姆

20pOd嘉泰姆

3pOd嘉泰姆

28pOd嘉泰姆

0.75pOd嘉泰姆

5pOd嘉泰姆

800pOd嘉泰姆

CXSD62107pOd嘉泰姆

TQFN3x3-16pOd嘉泰姆

COTpOd嘉泰姆

1pOd嘉泰姆

1pOd嘉泰姆

20pOd嘉泰姆

1.8pOd嘉泰姆

28pOd嘉泰姆

0.75pOd嘉泰姆

5pOd嘉泰姆

400pOd嘉泰姆

CXSD62108pOd嘉泰姆

QFN3.5x3.5-14pOd嘉泰姆

TQFN3x3-16pOd嘉泰姆

COTpOd嘉泰姆

1pOd嘉泰姆

1pOd嘉泰姆

20pOd嘉泰姆

1.8pOd嘉泰姆

28pOd嘉泰姆

0.75pOd嘉泰姆

5pOd嘉泰姆

400pOd嘉泰姆

CXSD62109pOd嘉泰姆

TQFN3x3-16pOd嘉泰姆

COTpOd嘉泰姆

1pOd嘉泰姆

2pOd嘉泰姆

20pOd嘉泰姆

1.8pOd嘉泰姆

28pOd嘉泰姆

0.75pOd嘉泰姆

5pOd嘉泰姆

400pOd嘉泰姆

CXSD62110pOd嘉泰姆

QFN3x3-20pOd嘉泰姆

TQFN3x3-16pOd嘉泰姆

COTpOd嘉泰姆

1pOd嘉泰姆

2pOd嘉泰姆

20pOd嘉泰姆

3pOd嘉泰姆

28pOd嘉泰姆

1.8|1.5|0.5pOd嘉泰姆

5pOd嘉泰姆

740pOd嘉泰姆

CXSD62111pOd嘉泰姆

TQFN4x4-24pOd嘉泰姆

|QFN3x3-20pOd嘉泰姆

CMpOd嘉泰姆

1pOd嘉泰姆

2pOd嘉泰姆

15pOd嘉泰姆

5pOd嘉泰姆

28pOd嘉泰姆

0.5pOd嘉泰姆

NpOd嘉泰姆

3000pOd嘉泰姆

CXSD62112pOd嘉泰姆

TDFN3x3-10pOd嘉泰姆

COTpOd嘉泰姆

1pOd嘉泰姆

1pOd嘉泰姆

20pOd嘉泰姆

1.8pOd嘉泰姆

28pOd嘉泰姆

0.5pOd嘉泰姆

5pOd嘉泰姆

250pOd嘉泰姆

CXSD62113|CpOd嘉泰姆

TQFN3x3-20pOd嘉泰姆

COTpOd嘉泰姆

1pOd嘉泰姆

2pOd嘉泰姆

15pOd嘉泰姆

6pOd嘉泰姆

25pOd嘉泰姆

2pOd嘉泰姆

NpOd嘉泰姆

550pOd嘉泰姆

CXSD62113EpOd嘉泰姆

TQFN 3x3 20pOd嘉泰姆

COTpOd嘉泰姆

2pOd嘉泰姆

2pOd嘉泰姆

11pOd嘉泰姆

6pOd嘉泰姆

25pOd嘉泰姆

2pOd嘉泰姆

NpOd嘉泰姆

550pOd嘉泰姆

CXSD62114pOd嘉泰姆

TQFN3x3-20pOd嘉泰姆

COTpOd嘉泰姆

2pOd嘉泰姆

2pOd嘉泰姆

11pOd嘉泰姆

5.5pOd嘉泰姆

25pOd嘉泰姆

2pOd嘉泰姆

NpOd嘉泰姆

280pOd嘉泰姆

CXSD62115pOd嘉泰姆

QFN4x4-24pOd嘉泰姆

VMpOd嘉泰姆

2pOd嘉泰姆

1pOd嘉泰姆

60pOd嘉泰姆

3.1pOd嘉泰姆

13.2pOd嘉泰姆

0.85pOd嘉泰姆

12pOd嘉泰姆

5000pOd嘉泰姆

CXSD62116A|B|CpOd嘉泰姆

SOP-8PpOd嘉泰姆

VMpOd嘉泰姆

1pOd嘉泰姆

1pOd嘉泰姆

20pOd嘉泰姆

2.9pOd嘉泰姆

13.2pOd嘉泰姆

0.8pOd嘉泰姆

12pOd嘉泰姆

16000pOd嘉泰姆

CXSD62117pOd嘉泰姆

SOP-20pOd嘉泰姆

VMpOd嘉泰姆

2pOd嘉泰姆

2pOd嘉泰姆

30pOd嘉泰姆

10pOd嘉泰姆

13.2pOd嘉泰姆

1pOd嘉泰姆

12pOd嘉泰姆

5000pOd嘉泰姆

CXSD62118pOd嘉泰姆

TDFN3x3-10pOd嘉泰姆

COTpOd嘉泰姆

1pOd嘉泰姆

1pOd嘉泰姆

25pOd嘉泰姆

1.8pOd嘉泰姆

28pOd嘉泰姆

0.7pOd嘉泰姆

5pOd嘉泰姆

250pOd嘉泰姆

CXSD62119pOd嘉泰姆

TQFN3x3-20pOd嘉泰姆

COTpOd嘉泰姆

2pOd嘉泰姆

1pOd嘉泰姆

40pOd嘉泰姆

1.8pOd嘉泰姆

25pOd嘉泰姆

REFIN SettingpOd嘉泰姆

5pOd嘉泰姆

700pOd嘉泰姆

CXSD62120pOd嘉泰姆

QFN 3x3 20pOd嘉泰姆

TQFN 3x3 16pOd嘉泰姆

COTpOd嘉泰姆

1pOd嘉泰姆

2pOd嘉泰姆

20pOd嘉泰姆

3pOd嘉泰姆

28pOd嘉泰姆

1.8|1.5 1.35|1.2 0.5pOd嘉泰姆

5pOd嘉泰姆

800pOd嘉泰姆

CXSD62121ApOd嘉泰姆

TQFN3x3 20pOd嘉泰姆

COTpOd嘉泰姆

1pOd嘉泰姆

2pOd嘉泰姆

15pOd嘉泰姆

3pOd嘉泰姆

28pOd嘉泰姆

0.75pOd嘉泰姆

5pOd嘉泰姆

220pOd嘉泰姆

CXSD62121BpOd嘉泰姆

TQFN3x3 20pOd嘉泰姆

COTpOd嘉泰姆

1pOd嘉泰姆

2pOd嘉泰姆

15pOd嘉泰姆

3pOd嘉泰姆

28pOd嘉泰姆

0.75pOd嘉泰姆

5pOd嘉泰姆

220pOd嘉泰姆

CXSD62121pOd嘉泰姆

TQFN3x3-20pOd嘉泰姆

COTpOd嘉泰姆

1pOd嘉泰姆

2pOd嘉泰姆

20pOd嘉泰姆

3pOd嘉泰姆

28pOd嘉泰姆

0.75pOd嘉泰姆

5pOd嘉泰姆

180pOd嘉泰姆

 pOd嘉泰姆

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