主动吸收2A持续电流接收器源总线终端高速线性调节器CXTP65160双数据率DDR存储系统中产生终端电压稳压器CXTP65161 CXTP65162
发表时间:2020-06-29
浏览次数:288

目录

1.产品概述       2.产品特点     JDh嘉泰姆

3.应用范围       4.技术规格书下载(PDF文档)JDh嘉泰姆

5.产品封装       6.电路原理图  JDh嘉泰姆

7.相关产品JDh嘉泰姆

   产品概述 返回TOPJDh嘉泰姆


The CXTP65162 CXTP65161 CXTP65160 is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 and SCSI-3 etc. devices requirements. The regulator is capable of actively sinking or sourcing up to 2A while regulating an output voltage to within 40mV. The output termination voltage cab be tightly regulated to track 1/2VDDQ by two external voltage divider resistors or the desired output voltage can be programmed by externally forcing the REFEN pin voltage. The CXTP65162 CXTP65161 CXTP65160 also incorporates a high-speed differential amplifier to provide ultra-fast response in line/load transient. Other features include extremely low initial offset voltage, excellent load regulation, current limiting in bi-directions and on-chip thermal shut-down protection. The CXTP65162 CXTP65161 CXTP65160 are available in the PSOP-8 (Exposed Pad) surface mount packages.

   产品特点 返回TOPJDh嘉泰姆


 Ideal for DDR-I, DDR-II and DDR-III VTT Applications JDh嘉泰姆

 Sink and Source 2A Continuous Current JDh嘉泰姆

 Integrated Power MOSFETJDh嘉泰姆

 Generates Termination Voltage for SSTL_2, SSTL _18, HSTL, SCSI-2 and SCSI-3 Interfaces. JDh嘉泰姆

 High Accuracy Output Voltage at Full-Load JDh嘉泰姆

 Output Voltage traces REFEN Pin Voltage. JDh嘉泰姆

 Low External Component Count JDh嘉泰姆

 Shutdown for Suspend to RAM (STR) Functionality with High-Impedance Output JDh嘉泰姆

 Current Limiting Protection JDh嘉泰姆

 Thermal Shutdown Protection JDh嘉泰姆

 PSOP-8 with exposed pad Pb-Free Package.JDh嘉泰姆

   应用范围 返回TOPJDh嘉泰姆


 Desktop PCs, Notebooks, and Workstations JDh嘉泰姆

 Graphics Card Memory Termination JDh嘉泰姆

 Set Top Boxes, Digital TVs, Printers JDh嘉泰姆

 Embedded Systems JDh嘉泰姆

 Active Termination Buses JDh嘉泰姆

 DDR-I, DDR-II and DDR-III Memory SystemsJDh嘉泰姆

   技术规格书(产品PDF) 返回TOP JDh嘉泰姆


     需要详细的PDF规格书请扫一扫微信联系我们,还可以获得免费样品以及技术支持JDh嘉泰姆

 QQ截图20160419174301.jpgJDh嘉泰姆

产品封装图 返回TOPJDh嘉泰姆


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电路原理图 返回TOPJDh嘉泰姆


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DDR Bus Termination Regulator(DDR总线终端稳压器)  JDh嘉泰姆

ProductJDh嘉泰姆

Status JDh嘉泰姆

Output Offset VoltageJDh嘉泰姆

Load Reg.JDh嘉泰姆

Max Sink& Source Current JDh嘉泰姆

VIN    MaxJDh嘉泰姆

Control Voltage RangeJDh嘉泰姆

CXTP65160JDh嘉泰姆

NRFND JDh嘉泰姆

±20mV JDh嘉泰姆

0.8%,1.2% JDh嘉泰姆

 3AJDh嘉泰姆

6V JDh嘉泰姆

3.3V to   6V JDh嘉泰姆

CXTP65161JDh嘉泰姆

Active JDh嘉泰姆

±20mVJDh嘉泰姆

0.50%JDh嘉泰姆

 1.5JDh嘉泰姆

6VJDh嘉泰姆

3.3V  to 6V JDh嘉泰姆

CXTP65162JDh嘉泰姆

Active JDh嘉泰姆

±20mV JDh嘉泰姆

0.50%JDh嘉泰姆

 2AJDh嘉泰姆

6VJDh嘉泰姆

3.3V to   6V JDh嘉泰姆