CXSD62125 1.5MHz高效单片同步降压稳压器电流模式设计陶瓷输出电容稳定单锂离子电池供电
发表时间:2020-04-25
浏览次数:120

目录OFc嘉泰姆

1.产品概述                       2.产品特点OFc嘉泰姆
3.应用范围                       4.下载产品资料PDF文档 OFc嘉泰姆
5.产品封装图                     6.电路原理图                   OFc嘉泰姆
7.功能概述                        8.相关产品OFc嘉泰姆

一,产品概述(General Description)         OFc嘉泰姆
       CXSD62125 CXSD62125A is a 1.5MHz high efficiency monolithic synchronous buck regulator.Design with current mode scheme,the CXSD62125 CXSD62125A is stable with ceramic output capacitor. Input voltage from 2.7V to 6.0V makes the CXSD62125 CXSD62125A ideally suited for single Li-Ion battery powered OFc嘉泰姆

applications. 100%duty cycle provides low dropout operation, extending battery OFc嘉泰姆

life in portable electrical devices.The internally fixed 1.5MHz operating frequencyOFc嘉泰姆

 allows the using of small surface mount inductors and capacitors. The synchronous switches included inside increase the efficiency and eliminate the need of an external Schottky diode.OFc嘉泰姆

The CXSD62125 CXSD62125A is available in SOT-23-5/TSOT-23-5A packages.OFc嘉泰姆
二.产品特点(Features)OFc嘉泰姆
1A Output CurrentOFc嘉泰姆
Wide 2.7V~6.0V Input VoltageOFc嘉泰姆
Fixed 1.5MHz Switching FrequencyOFc嘉泰姆
Low Dropout Operating at 100% Duty CycleOFc嘉泰姆
25μA Quiescent CurrentOFc嘉泰姆
Integrate Synchronous RectifierOFc嘉泰姆
0.6V Reference VoltageOFc嘉泰姆
Current-Mode Operation with InternalOFc嘉泰姆
CompensationOFc嘉泰姆
- Stable with Ceramic Output CapacitorsOFc嘉泰姆
- Fast Line Transient ResponseOFc嘉泰姆
Short-Circuit ProtectionOFc嘉泰姆
Over-Temperature Protection with HysteresisOFc嘉泰姆
Available in SOT-23-5/TSOT-23-5A PackagesOFc嘉泰姆
Lead Free and Green Devices Available (RoHS Compliant)OFc嘉泰姆
三,应用范围 (Applications)OFc嘉泰姆

HD STBOFc嘉泰姆

BT MouseOFc嘉泰姆
PND InstrumentOFc嘉泰姆
Portable InstrumentOFc嘉泰姆
四.下载产品资料PDF文档 OFc嘉泰姆

需要详细的PDF规格书请扫一扫微信联系我们,还可以获得免费样品以及技术支持OFc嘉泰姆

 QQ截图20160419174301.jpgOFc嘉泰姆

五,产品封装图 (Package)OFc嘉泰姆

blob.pngOFc嘉泰姆

六.电路原理图OFc嘉泰姆

blob.pngOFc嘉泰姆

七,功能概述OFc嘉泰姆


In most applications, the CXSD62125 CXSD62125A does not dissipate much heat due to its high efficiency. But, in applications where the CXSD62125 CXSD62125A is running at high ambient tempera ture with low supply voltage and high duty cycles, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches ap-proximately 150°C, both power switches will be turned off and the SW node will become high impedance.To avoid the CXSD62125 CXSD62125A from exceeding the maximum junction temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maxi-mum junction temperature of the part. The power dissipated by the part is approximated:OFc嘉泰姆
PD ≅ IOUT2 x (RP-FET x D+RN-FET x (1-D))OFc嘉泰姆
The temperature rise is given by:OFc嘉泰姆
TR = (PD)(èJA)OFc嘉泰姆
Where PD is the power dissipated by the regulator, D isOFc嘉泰姆
duty cycle of main switchOFc嘉泰姆
D = VOUT/VINOFc嘉泰姆
The èJA is the thermal resistance from the junction of theOFc嘉泰姆
die to the ambient temperature. The junction temperature,OFc嘉泰姆
TJ, is given by:OFc嘉泰姆
TJ = TA + TROFc嘉泰姆
Where TA is the ambient temperature.
Layout ConsiderationOFc嘉泰姆
For all switching power supplies, the layout is an important step in the design; especially at high peak currentsOFc嘉泰姆
and switching frequencies. If the layout is not carefully done, the regulator might show noise problems and dutyOFc嘉泰姆
cycle jitter.OFc嘉泰姆
1. The input capacitor should be placed close to the VIN and GND. Connecting the capacitor and VIN/GND withOFc嘉泰姆
short and wide trace without any via holes for good input voltage filtering. The distance between VIN/GNDOFc嘉泰姆
to capacitor less than 2mm respectively is recommended.OFc嘉泰姆
2. To minimize copper trace connections that can inject noise into the system, the inductor should be placedOFc嘉泰姆
as close as possible to the SW pin to minimize the noise coupling into other circuits.OFc嘉泰姆
3. The output capacitor should be place closed to converter VOUT and GND.OFc嘉泰姆
4. Since the feedback pin and network is a high impedance circuit the feedback network should be routedOFc嘉泰姆
away from the inductor. The feedback pin and feedback network should be shielded with a ground planeOFc嘉泰姆
or trace to minimize noise coupling into this circuit.OFc嘉泰姆
5. A star ground connection or ground plane minimizes ground shifts and noise is recommended.OFc嘉泰姆
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