目录Q3p嘉泰姆

1.产品概述                       2.产品特点Q3p嘉泰姆
3.应用范围                       4.下载产品资料PDF文档 Q3p嘉泰姆
5.产品封装图                     6.电路原理图                   Q3p嘉泰姆
7.功能概述                        8.相关产品Q3p嘉泰姆

一,产品概述(General Description)    Q3p嘉泰姆

  The CXSD62115, two-phase PWM control IC, provides a precision voltage regulation system for advanced graphic microprocessors in graphics card applications. The inte-gration of power MOSFET drivers into the controller ICQ3p嘉泰姆
reduces the number of external parts for a cost and space saving power management solution.Q3p嘉泰姆
  The CXSD62115 uses a voltage-mode PWM architecture,operating with fixed-frequency, to provide excellent load transient response. The device uses the voltage across the DCRs of the inductors for current sensing. Load lineQ3p嘉泰姆
voltage positioning (DROOP), channel-current balance,and over-current protection are accomplished through continuous inductor DCR current sensing.Q3p嘉泰姆
The MODE pin programs single- or two- phase operation.When IC operates in two-phase mode normally, it can transfer two-phase mode to single phase mode at liberty.Nevertheless, once operates in single-phase mode, the operation mode is latched. It is required to toggle SS or 5VCC pin to reset the IC. Such feature of the MODE pin makes the CXSD62115 ideally suitable for dual power input applications, such as PCIE interfaced graphic cards. This control IC‘s protection features include a set of so- phisticated over-temperature, over-voltage, under-voltage, and over-current protections. Over-voltage results in the converter turning the lower MOSFETs on to clamp the rising output voltage and protects the microprocessor.The over-current protection level is set through externalresistors. The device also provides a power-on-reset func-tion and a programmable soft-start to prevent wrong op-eration and limit the input surge current during power-on or start-up.Q3p嘉泰姆
 The CXSD62115 is available in a QFN4x4-24A packageQ3p嘉泰姆
二.产品特点(Features)Q3p嘉泰姆

Voltage-Mode Operation with Current SharingQ3p嘉泰姆
- Adjustable Feedback CompensationQ3p嘉泰姆
- Fast Load Transient ResponseQ3p嘉泰姆
Operate with 8V~13.2 VCC Supply VoltageQ3p嘉泰姆
Programmable 3-Bit DAC ReferenceQ3p嘉泰姆
-±1.5% System Accuracy Over-TemperatureQ3p嘉泰姆
Support Single- and Two-Phase OperationsQ3p嘉泰姆
5V Linear Regulator Output on 5VCCQ3p嘉泰姆
8~12V Gate Drivers with Internal Bootstrap DiodeQ3p嘉泰姆
Lossless Inductor DCR Current SensingQ3p嘉泰姆
Fixed 300kHz Operating Frequency Per PhaseQ3p嘉泰姆
Power-OK Indicator OutputQ3p嘉泰姆
- Regulated 1.5V on POKQ3p嘉泰姆
Adjustable Over-Current Protection (OCP)Q3p嘉泰姆
Accurate Load Line (DROOP) ProgrammingQ3p嘉泰姆
Adjustable Soft-StartQ3p嘉泰姆
Over-Voltage Protection (OVP)Q3p嘉泰姆
Under-Voltage Protection (UVP)Q3p嘉泰姆
Over-Temperature Protection (OTP)Q3p嘉泰姆
QFN4x4 24-Lead Package (QFN4x4-24A)Q3p嘉泰姆
Lead Free and Green Devices AvailableQ3p嘉泰姆
(RoHS Compliant)Q3p嘉泰姆
三,应用范围 (Applications)Q3p嘉泰姆

Graphics Card GPU Core Power SupplyQ3p嘉泰姆

Motherboard Chipset or DDR SDRAM Core Power SupplyQ3p嘉泰姆
On-Board High Power PWM Converter withQ3p嘉泰姆

Output Current up to 60AQ3p嘉泰姆
四.下载产品资料PDF文档 Q3p嘉泰姆

需要详细的PDF规格书请扫一扫微信联系我们，还可以获得免费样品以及技术支持！Q3p嘉泰姆

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五,产品封装图 (Package)Q3p嘉泰姆

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六.电路原理图Q3p嘉泰姆

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七,功能概述Q3p嘉泰姆

Layout Consideration Q3p嘉泰姆

In any high switching frequency converter, a correct lay-out is important to ensure proper operation of theQ3p嘉泰姆
regulator. With power devices switching at higher frequency, the resulting current transient will cause volt-Q3p嘉泰姆
age spike across the interconnecting impedance and parasitic circuit elements. As an example, consider theQ3p嘉泰姆
turn-off transition of the PWM MOSFET. Before turn-off condition, the MOSFET is carrying the full load current.Q3p嘉泰姆
During turn-off, current stops flowing in the MOSFET and is freewheeling by the lower MOSFET and parasitic diode.Q3p嘉泰姆
Any parasitic inductance of the circuit generates a large voltage spike during the switching interval. In general,Q3p嘉泰姆
using short and wide printed circuit traces should mini-mize interconnecting impedances and the magnitude ofQ3p嘉泰姆
voltage spike. And signal and power grounds are to be kept separating and finally combined to use the groundQ3p嘉泰姆
plane construction or single point grounding. The best tie-point between the signal ground and the power ground is at the negative side of the output capacitor on each channel, where there is less noise. Noisy traces beneath the IC are not recommended. Below is a checklist for your layout:Q3p嘉泰姆
close their pins. (For example, place the decoupling ce-ramic capacitor near the drain of the high-side MOSFETQ3p嘉泰姆
as close as possible. The bulk capacitors are also placed near the drain).Q3p嘉泰姆
- The input capacitor should be near the drain of the up-per MOSFET; the high quality ceramic decoupling capaci-tor can be put close to the VCC and GND pins; the VTTREF decoupling capacitor should be close to the VTTREF pin and GND; the VDDQ and VTT output capacitors should be located right across their output pin as close as pos-sible to the part to minimize parasitic. The input capacitor GND should be close to the output capacitor GND and the lower MOSFET GND.Q3p嘉泰姆
- The drain of the MOSFETs (VIN and PHASE nodes) should be a large plane for heat sinking. And PHASE pinQ3p嘉泰姆
traces are also the return path for UGATE. Connect this pin to the converter’s upper MOSFET source.Q3p嘉泰姆
- The CXSD62115 used ripple mode control. Build the re- sistor divider close to the VFB pin so that the high imped- ance trace is shorter. And the VFB pin traces can’t be closed to the switching signal traces (UGATE, LGATE,BOOT, and PHASE).Q3p嘉泰姆
- The PGND trace should be a separate trace, and inde-pendently go to the source of the low-side MOSFETs forQ3p嘉泰姆
current limit accuracy.Q3p嘉泰姆

Layout ConsiderationQ3p嘉泰姆
- Keep the switching nodes (UGATE, LGATE, BOOT, and PHASE) away from sensitive small signal nodes(VFB,VTTREF, and CS) since these nodes are fast moving signals. Therefore, keep traces to these nodes as short as possible and there should be no other weak signal traces in parallel with theses traces on any layer.Q3p嘉泰姆
- The signals going through theses traces have both high dv/dt and high di/dt, with high peak charging and dis-charging current. The traces from the gate drivers to the MOSFETs (UGATE and LGATE) should be short and wide.Q3p嘉泰姆
- Place the source of the high-side MOSFET and the drain of the low-side MOSFET as close as possible. Minimiz-ing the impedance with wide layout plane between the two pads reduces the voltage bounce of the node.Q3p嘉泰姆

- Decoupling Q3p嘉泰姆

 capacitor, the resistor dividers, boot capacitors, and current limit stetting resistor should beQ3p嘉泰姆

CXSD62115Q3p嘉泰姆

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