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目录 1.产品概述 2.产品特点 一,产品概述(General Description) The CXSD62104 integrates dual step-down, constant-ontime, synchronous PWM controllers (that drives dual N-channel MOSFETs for each channel) and provide up to 100mA output current. When the PWMx output voltage is higher than LDOx bypass threshold, the related LDOx regulator is shut off and its output is connected to VOUTx by internal switchover MOSFET. It can save power dissipation. output voltage in either PFM or PWM Mode.In Pulse-Frequency Mode (PFM), the CXSD62104 provides very high efficiency over light to heavy loads with loading-modulated switching frequencies. The Forced-PWM mode works nearly at constant frequency for low-noise requirements. The unique ultrasonic mode maintains the switching frequency above 25KHz, which eliminates noise in audio applications. The CXSD62104 is equipped with accurate sourcing cur-rent-limit, output under-voltage and output over-voltage protections, being perfect for NB applications. A 1.7ms (typ.) digital soft-start can reduce the start-up current. A soft-stop function actively discharges the output capaci-tors by the discharge device. The CXSD62104 has individual enable controls for PWM channels and LDOs. Pulling both ENPWM pin and ENLDO pin low shuts down the whole chip with low quiescent current close to zero. 70% Under-Voltage and 125% Over-Voltage Protec-tions (PWM) Adjustable Current-Limit Protection (PWMs) 三,应用范围 (Applications) Notebook and Sub-Notebook Computers Portable Devices 四.下载产品资料PDF文档 |
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五,产品封装图 (Package)
六.电路原理图
七,功能概述
Input Capacitor Selection
The input capacitor is chosen based on the voltage rating and the RMS current rating. For reliable operation, select
the capacitor voltage rating to be at least 1.3 times higher than the maximum input voltage. The maximum RMS
current rating requirement is approximately IOUT/2, where IOUT is the load current. During power up, the input capaci-tors have to handle large amount of surge current. In low-duty notebook appliactions, ceramic capacitors are
remmended. The capacitors must be connected between the drain of high-side MOSFET and the source of low-
side MOSFET with very low-impeadance PCB layout.
MOSFET Selection
The application for a notebook battery with a maximum volt-age of 24V, at least a minimum 30V MOSFETs should
be used. The design has to trade off the gate charge with the RDS(ON) of the MOSFET:
· For the low-side MOSFET, before it is turned on, the body diode has been conducted. The low-side MOSFET
driver will not charge the miller capacitor of this MOSFET.
In the turning off process of the low-side MOSFET,the load current will shift to the body diode first. The
high dv/dt of the phase node voltage will charge the miller capacitor through the low-side MOSFET driver
sinking current path. This results in much less switching loss of the low-side MOSFETs. The duty
cycle is often very small in high battery voltage applications, and the low-side MOSFET will con-
duct most of the switching cycle; therefore, the less the RDS(ON) of the low-side MOSFET, the less the power
loss. The gate charge for this MOSFET is usually a secondary consideration. The high-side MOSFET
does not have this zero voltage switching condition, and because it conducts for less time
compared to the low-side MOSFET, the switching loss tends to be dominant. Priority should be given
to the MOSFETs with less gate charge, so that both the gate driver loss and switching loss will be minimized.
The selection of the N-channel power MOSFETs are de-termined by the RDS(ON), reversing transfer capacitance
(CRSS) and maximum output current requirement. The losses in the MOSFETs have two components: conduc-
tion loss and transition loss. For the high-side and low-side MOSFETs, the losses are approximately given by
the following equations:
Layout Consideration
In any high switching frequency converter, a correct layout is important to ensure proper operation of the regulator.
With power devices switching at higher frequency, the resulting current transient will cause voltage spike across
the interconnecting impedance and parasitic circuit elements. As an example, consider the turn-off transition
of the PWM MOSFET. Before turn-off condition, the MOSFET is carrying the full load current. During turn-off,
current stops flowing in the MOSFET and is freewheeling by the lower MOSFET and parasitic diode. Any parasitic
inductance of the circuit generates a large voltage spike during the switching interval. In general, using short and
wide printed circuit traces should minimize interconnect-ing impedances and the magnitude of voltage spike. And
signal and power grounds are to be kept separating and finally combined to use the ground plane construction or
single point grounding. The best tie-point between the signal ground and the power ground is at the negative
side of the output capacitor on each channel, where there is less noise. Noisy traces beneath the IC are not
recommended. Below is a checklist for your layout:
Layout Consideration (Cont.)
Keep the switching nodes (UGATEx, LGATEx, BOOTx,and PHASEx) away from sensitive small signal nodes
(REF, ILIMx, and FBx) since these nodes are fast mov-ing signals. Therefore, keep traces to these nodes as
short as possible and there should be no other weak signal traces in parallel with theses traces on any layer.
Minimizing the impedance with wide layout plane be-tween the two pads reduces the voltage bounce of
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Switching Regulator > Buck Controller |
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Part_No |
Package |
Archi tectu |
Phase |
No.of PWM Output |
Output Current (A) |
Input Voltage (V) |
Reference Voltage (V) |
Bias Voltage (V) |
Quiescent Current (uA) |
|
|
min |
max |
|||||||||
|
SOP-14 QSOP-16 QFN4x4-16 |
VM |
1 |
1 |
30 |
2.9 |
13.2 |
0.9 |
12 |
8000 |
|
|
SOP-8 |
VM |
1 |
1 |
20 |
2.9 |
13.2 |
0.8 |
12 |
5000 |
|
|
SOP-8 |
VM |
1 |
1 |
20 |
2.9 |
13.2 |
0.8 |
12 |
5000 |
|
|
QFN4x4-24 |
VM |
2 |
1 |
60 |
3.1 |
13.2 |
0.6 |
12 |
5000 |
|
|
SOP-8 |
VM |
1 |
1 |
20 |
2.2 |
13.2 |
0.8 |
5~12 |
2100 |
|
|
SOP-8 |
VM |
1 |
1 |
20 |
2.2 |
13.2 |
0.8 |
5~12 |
2100 |
|
|
SOP8|TSSOP8 |
VM |
1 |
1 |
5 |
5 |
13.2 |
1.25|0.8 |
5~12 |
3000 |
|
|
SOP-8 |
VM |
1 |
1 |
10 |
3.3 |
5.5 |
0.8 |
5 |
2100 |
|
|
SOP-14 |
VM |
1 |
1 |
10 |
5 |
13.2 |
0.8 |
12 |
2000 |
|
|
TSSOP-24 |QFN5x5-32 |
VM |
1 |
2 |
20 |
5 |
13.2 |
0.6 |
5~12 |
4000 |
|
|
SOP14 QSOP16 QFN-16 |
VM |
1 |
1 |
30 |
2.9 |
13.2 |
0.9 |
12 |
4000 |
|
|
SOP-14 |
VM |
1 |
1 |
30 |
2.2 |
13.2 |
0.6 |
12 |
5000 |
|
|
SOP-14 |
VM |
1 |
1 |
30 |
2.2 |
13.2 |
0.6 |
12 |
5000 |
|
|
SOP-14 |
VM |
1 |
1 |
25 |
2.2 |
13.2 |
0.8 |
12 |
5000 |
|
|
LQFP7x7 48 TQFN7x7-48 |
VM |
1 |
6 |
0.015 |
1.4 |
6.5 |
- |
5 |
1800 |
|
|
TSSOP-24P |
VM |
1 |
2 |
20 |
2.97 |
5.5 |
0.8 |
5~12 |
5000 |
|
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