CXSD6282A关闭和软启动功能电压型PWM控制设计欠压保护（UVP）过电流保护（OCP）

目录9ri嘉泰姆

1.产品概述         2.产品特点9ri嘉泰姆
3.应用范围       4.下载产品资料PDF文档 9ri嘉泰姆
5.产品封装图                     6.电路原理图             9ri嘉泰姆
7.功能概述       8.相关产品9ri嘉泰姆

一,产品概述(General Description) 9ri嘉泰姆

The CXSD6282 CXSD6282A is a voltage mode, synchronous PWM controller which9ri嘉泰姆
drives dual N-channel MOSFETs. The device integrates all of the control, monitoring and protecting functions into a single package, provides one controlled power output with under-voltage and over-current protections.The CXSD6282 CXSD6282A provides excellent regulation for output load variation. The internal 0.6V temperature-compensated reference voltage is designed to meet the requirement of low output voltage applications. The device includes a 200kHz free-running triangle-wave oscillator that is adjustable from 50kHz to 1000kHz.9ri嘉泰姆
The CXSD6282 CXSD6282A has been equipped with excellent protec-tion functions: POR, OCP, and UVP. The Power-On-Re-set (POR) circuit can monitor the VCC, EN, and OCSET voltage to make sure the supply voltage exceeds their threshold voltage while the controller is running. The Over-Current Protection (OCP) monitors the output cur-rent by using the voltage drop across the upper MOSFET’s RDS(ON). When the output current reaches the trip point, the controller will run the soft-start function until the fault events are removed. The Under-Voltage Protection (UVP)monitors the voltage at FB pin (V FB) for short-circuit protection. When the VFB is less than 50% of VREF, the controller will shutdown the IC directly. 9ri嘉泰姆
二.产品特点(Features)9ri嘉泰姆

1.)Single 12V Power Supply Required9ri嘉泰姆
2.)0.6V Reference with 1% Accuracy9ri嘉泰姆
3.)Shutdown and Soft-Start Function9ri嘉泰姆
4.)1.)Programmable Frequency Range from 50 kHz to 1000kHz9ri嘉泰姆
5.)Voltage Mode PWM Control Design9ri嘉泰姆
6.)Up to 100% Duty Cycle9ri嘉泰姆
7.)Under-Voltage Protection (UVP)9ri嘉泰姆
8.)Over-Current Protection (OCP) SOP-14 Package9ri嘉泰姆
9.)Lead Free and Green Devices Available (RoHS Compliant)9ri嘉泰姆
三,应用范围 (Applications)9ri嘉泰姆

Graphic Cards9ri嘉泰姆
四.下载产品资料PDF文档 9ri嘉泰姆

需要详细的PDF规格书请扫一扫微信联系我们，还可以获得免费样品以及技术支持！9ri嘉泰姆

QQ截图20160419174301.jpg 9ri嘉泰姆

9ri嘉泰姆

五,产品封装图 (Package)9ri嘉泰姆

六.电路原理图

七,功能概述

Layout Consideration
In any high switching frequency converter, a correct layout is important to ensure proper operation
of the regulator.With power devices switching at 300kHz,the resulting cur-rent transient will cause
voltage spike across the i n t e r c o n n e c t i n g impedance and parasitic circuit elements. As an
example, consider the turn-off transition of the PWM MOSFET. Before turn-off, the MOSFET is
carrying the full load current. During turn-off, current stops flowing in the MOSFET and is
free-wheeling by the lower MOSFET and parasitic diode. Any parasitic inductance of the circuit
generates a large voltage spike during the switching interval. In general, using short and
wide printed circuit traces should minimize interconnect-ing impedances and the magnitude
of voltage spike.And signal and power grounds are to be kept separating till combined using
the ground plane construction or single point grounding. Figure 10 illustrates the layout,
with bold lines indicating high current paths; these traces must be short and wide. Components
along the bold lines should be placed lose together. Below is a checklist for your layout:
- Keep the switching nodes (UGATE, LGATE, and PHASE) away from sensitive small signal nodes
since these nodes are fast moving signals. Therefore,keep traces to these nodes as short as possible.
- The traces from the gate drivers to the MOSFETs (UGATE, LGATE) should be short and wide.
- Place the source of the high-side MOSFET and the drain of the low-side MOSFET as close as possible.
Minimizing the impedance with wide layout plane between the two pads reduces the voltage bounce of
the node.
- Decoupling capacitor, compensation component, the resistor dividers, boot capacitors, and SS capacitors
should be close their pins. (For example, place the decoupling ceramic capacitor near the drain of the
high-side MOSFET as close as possible. The bulk capacitors are also placed near the drain).
- The input capacitor should be near the drain of the upper MOSFET; the output capacitor should be near
the loads. The input capacitor GND should be close to the output capacitor GND and the lower MOSFET
GND.
- The drain of the MOSFETs (VIN and PHASE nodes)should be a large plane for heat sinking.

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